Operational trans conductance amplifier working

Hi

Can some one help me in understanding this OTA confguration. I have seen different OTA configuration but this OTA configuration attached below has three current mirrors to pass the current to the output. What about the ac current? I think current mirrors work for DC currents then how will ac current appear at output?

ICdesignerbeginner said:

... I think current mirrors work for DC currents ...

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Wrong: they operate as their name tells: they mirror (actually: copy) current, regardless of DC or ac .

thank you for your reply.

can you please help me in understanding If all the three current mirror currents are same then it means the output current will be zero? AC and DC both?

ICdesignerbeginner said:

If all the three current mirror currents are same then it means the output current will be zero? AC and DC both?

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Why zero? The DC current injected by the DC current source ISS is copied (possibly multiplied) via M9 to M10, one half of this current is copied by the mirror M3->M5 to the mirror M7->M8, the other half via the mirror M4->M6. This results in a DC current equal to one half of the current through M10 (if no current multiplication by the mirrors has to be considered).

Injected ac currents by the impedances of M1 & M2 - amplified by the OTA transistors M1 .. M4 - will equally be mirrored via M3->M5->M7->M8, as well as M4->M6, where the ac output voltage vout is generated via the transimpedances of M6 & M8 . The ac OTA currents through M1-M3 and M2-M4 are anti-phase, so they will be added.

DC currents generated (copied) by mirrors are reproduced as absolute (fixed) values, hence will not be added by such mirror circuits - there's no anti-phase current generation as by the OTA transistors M1 .. M4 (DC currents have the same direction).

Thank you erikl for your detailed reply. I understand all your described working of OTA but I was saying about output zero for DC because let suppose I have 10u amp ISS and 5u A passing through M1 and M3, similarly 5u A passing through M2 and M4 the same 5uA current is copied from M3 and M5 - M7 to M8. It means 5uA current is flowing through the drain of M8. Similarly 5uA is flowing through M4 to M6. It means 5uA is flowing through the drain of M6. Now if 5uA flowing through M8 is flowing down to M6 then it means no current is flowing out of the OTA. then DC current is zero.

This type of current mirrors are class AB structures. Am I right?

This type of current mirrors are class AB structures. Am I right?

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Class AB or class B are classifications for bipolar amplifier output stages and not applicable to unipolar current sources.

The OTA signal path is actually implemented as pure class A.

ICdesignerbeginner said:

... Now if 5uA flowing through M8 is flowing down to M6 then it means no current is flowing out of the OTA. then DC current is zero.

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This is correct if you have only a capacitive load (e.g. CMOS gate(s)). A resistive load would of course draw an appropriate DC current, which, by this, would change the output operation point voltage.

I have attached a schematic. M17-M20 are invertig the current how is it inverting. Is it inverting the ac current? or Dc? M12, M14, M15 and M16 is producing positive current io+ and M17-M20 is producing negative current io-. I cant underatnd how is this happening. The current comming from the load transistors ar now coming from the source transistors thats why? or is there any other reason?

ICdesignerbeginner said:

M17-M20 are invertig the current how is it inverting.

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They don't invert.

ICdesignerbeginner said:

Is it inverting the ac current?

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No, not the transistors. The ac current "inversion" is evoked by feeding a (e.g.) VDD-referenced ac current from the upper PMOS to the lower NMOS, where this very same ac current gets GND-referenced, which causes the "inversion" (same current, but now referenced to the opposite terminal).

ICdesignerbeginner said:

or Dc?

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No, if you think of absolute value, or current direction. Of course you could say: VDD via the PMOS sources the current, and the NMOS sinks the current to GND. If you refer this (same) current to its associated terminal, so it's sourced by VDD and sunk by GND, which you also might consider as inversion, like in the ac case.

ICdesignerbeginner said:

M12, M14, M15 and M16 is producing positive current io+ and M17-M20 is producing negative current io-

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Here, we must differentiate between the DC & the ac path:

The mirror master M11 from the left Vi- branch reproduces its both DC & ac currents (possibly multiplied by the ratio of the W/L ratios of the involved MOSFETs) by mirror slave M12, which feeds these currents to NMOS mirror master M15, which - on its part - feeds this same current to NMOS mirror slave M16. The PMOS mirror master M13 from the right Vi+ branch via the PMOS mirror slave M14 closes this DC path.

The ac current part from the left Vi- branch (let's call it i_-) via M11 & M12-M15-M16 arrives inverted (GND-referenced) as -i_- at node Io1, whereas the ac current part from the right Vi+ branch (i₊) - which is inverted itself compared to the left part - arrives via M13-M14 non-inverted as i₊ at node Io1, where they get added:
-i_- + i₊ = i₊ - i_- = 2i₊ (as i_- = -i₊).

Similar argumentation applies to the Io2 node.

ICdesignerbeginner said:

The current comming from the load transistors ar now coming from the source transistors thats why?

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It's the same current, s. above!