[SOLVED] operational amplifier layout error

i draw the layout of op amp. its
DRC clean
LVS clean
But when i simulate the extracted file from layout i got the gain of op amp in negative a

The gain from the inverting input to the output is negative, of course.

You do not say if the schematic-tree version works the
same, or different (grossly or matter of degree). That is
the first thing to check, substituting only the config of
the op amp (if you had two distinct branches of hierarchy,
perhaps even running the two side-by-side could enable
some debugging).

But I have also found that the more sophisticated tools
(stb) will occasionally give whacked or broken results
while a simple ac simulation and post-plotting gives sane
ones for the same conditions; I think this is the initial
conditions coming up wrong, but I seldom bother to find
out, I've given up on stb and use methods I've found to
be less whimsical / brittle. So I recommend that you look
to the AC analysis, plot db(Aout/Ain) and phase(Aout-Ain)
and inspect for normalcy. And be sure your Ain is not the
source ampliture, but the pin difference voltage, turned
into a magnitude at the end - I like a vcvs to probe that
and make a VID node I can get at, not let the canned
routine think for itself.

I assume that You get open loop gain below 0dB. Check on the netlist are You have all pins well extracted. Long time ago Assura 3.1 has sometimes problems to extracted global pins like vdda! or gnd!.

Thanks all for reply...There is problem in extracted netlist now my problem is solved.