Operational amplifier in VerilogA.

[Tõnn]

Hy,

I have to use vdd and gnd to limit the output voltage of operational amplifier. I need to do that in VerilogA. I found some example how to do it in specific value but I do not understand how can I use vdd and gnd for that. Example is in **broken link removed**.

 

[micro designer]

in the code vout_max is actually Vdd - gnd and vout_min is Vss-gnd where Vdd=10V and Vss=-10V
hope this helps

 

[Superweasel]

Hi,

Sorry for hijacking the thread but I have similar problem. As Im newbie maybe somone could give good hints for solving the problem.

So, Im also trying to make simple OpAmp in Verilog-A, which would have output limitations (eg. from Vss to Vdd). In other words even when the output of my opamp is higer or lower, it still wouldnt exceed my max. /min. limitations.


Firstly, I have tried example provided by Tõnn in his first post, but my simulator does not like it. No compile errors, but still it doesnt work in the way it should.

Secondly, I solved the problem in the way showed below. The problem is it works when there is few components in schematic, but using lots of them the simulator gets slower and slower. Probably again convergence issue as there are still "sharp edges" and the function isnt continous enough.

module dif_amp(out,ref,inp,inm) ;
electrical out,ref,inp,inm ;
parameter real GAIN_V=10000 ;
parameter real Vmax=5 ;
parameter Vmin=-5 ;

analog begin

if (V(out,ref) > Vmax) V(out,ref) <+ Vmax+0.0001*V(inp,inm) ;
else
if (V(out,ref) < Vmin) V(out,ref) <+ Vmin+0.0001*V(inp,inm) ;
else
V(out,ref) <+ GAIN_V*V(inp,inm) ;

end

endmodule

Looking forward to your help.