it_boy
Full Member level 3
If anybody has used opencores pci bridge core, please help me. I am finding that the frame signal from the core is not according to the specification.
When the core is acting as a target, it is expecting the frame to be asserted for the cycle in which the last data.
Has anybody else faced such problems? Are any changes necessary to make it work on the board?
When the core is acting as a target, it is expecting the frame to be asserted for the cycle in which the last data.
Has anybody else faced such problems? Are any changes necessary to make it work on the board?