Open loop settings??

pekachoo007 · Oct 12, 2015

Is this setting valid for finding the Open loop gain of the opamp.

If yes then hows its done in cadence spectre.

FvM · Oct 12, 2015

There must be no OP capacitive output load, remove one capacitor.

Use high L and C values, e.g. 1000 H / 1000F or higher, depending on the frequency range of interest.

pekachoo007 · Oct 12, 2015

FvM said:
There must be no OP capacitive output load, remove one capacitor.

The opamp is actually an error amplifier part of a linear voltage regulator. The output capacitance represents the gate capacitance of pass transistor.

FvM said:
Use high L and C values, e.g. 1000 H / 1000F or higher, depending on the frequency range of interest.

Using 10^12H and 10^12F for L and C values for the frequency of operation of 10MHz.

AMS012 · Oct 12, 2015

A small question. Why do you need inductance in feed back? Can't you directly connect the -ve terminal of the opamp to the required DC potential and measure the open loop gain? Correct me if I am wrong.

FvM · Oct 12, 2015

The opamp is actually an error amplifier part of a linear voltage regulator. The output capacitance represents the gate capacitance of pass transistor.

^
O.K., in this case the regular output C should be used.

pekachoo007 · Oct 12, 2015

What settings should I give to Cadence Spectre for simulation results of gain and phase margin

erikl · Oct 12, 2015

Run an ac simulation for your frequency range of interest, then display gain (dB20 scale) and phase.

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AMS012 said:
Why do you need inductance in feed back? Can't you directly connect the -ve terminal of the opamp to the required DC potential and measure the open loop gain?

Because you need the DC control loop.

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pekachoo007 said:
Using 10^12H and 10^12F for L and C values for the frequency of operation of 10MHz.

Calculate its cutoff frequency resp. time constant! DC control will take much too long for your simulation period: don't forget the output impedance of the opAmp.

pekachoo007 · Oct 13, 2015

erikl said:
Run an ac simulation for your frequency range of interest, then display gain (dB20 scale) and phase.

I have done this but not satisfied with results.

erikl said:
Calculate its cutoff frequency resp. time constant! DC control will take much too long for your simulation period: don't forget the output impedance of the opAmp.

What would be use of these extra calculation, how they would be helpful. As you suggested, could you provide the formulas also.

LvW · Oct 13, 2015

pekachoo007 said:
I have done this but not satisfied with results.

Nice information - but not very helpful for us.
If you really need help you should tell us what you have done and what the results are.

pekachoo007 · Oct 13, 2015

Set AC source with AC Magnitude=1 V, DC Voltage=1.1 V, f=10 MHz

db20 = 44 db
What would be phase Margin, is it 180-67= 113??

erikl · Oct 13, 2015

pekachoo007 said:
What would be use of these extra calculation, how they would be helpful. As you suggested, could you provide the formulas also.

Just use the known or estimated value of the opAmp's DC output resistance R and calculate the cutoff frequency of this low-pass filter RLC time constant; its inverse is the time constant of your DC input control voltage, i.e. before this time you can't expect to get the correct input bias.

At this cutoff frequency you can neglect the value of your chosen L=10^12H impedance against the opAmp's DC output resistance R value - let's say this is 100Ω - so the cutoff frequency - considering your chosen C=10^12F value - fco = 1/(2πRC) =0.16*10^-14 Hz, its time constant is τ = 2πRC = 6.28*10^14 s ≈ 20 million years. After this time you can expect that the input bias has reached about 63% of its correct value, more than 99% after 5τ ≈ 100 million years.

FvM · Oct 13, 2015

before this time you can't expect to get the correct input bias

SPICE achieves a correct bias point in "no time" because it disables all Ls and Cs during initial transient solution.

erikl · Oct 13, 2015

pekachoo007 said:
What would be phase Margin, is it 180-67= 113??

No: 67° , the distance to 0° if the phase start is at 180°.

LvW · Oct 13, 2015

pekachoo007, is the max. gain of 40 dB the value you have expected?
Why a dc voltage of 1.1 V ?

pekachoo007 · Oct 14, 2015

erikl said:
At this cutoff frequency you can neglect the value of your chosen L=10^12H impedance against the opAmp's DC output resistance R value - let's say this is 100Ω - so the cutoff frequency - considering your chosen C=10^12F value - fco = 1/(2πRC) =0.16*10^-14 Hz, its time constant is τ = 2πRC = 6.28*10^14 s ≈ 20 million years. After this time you can expect that the input bias has reached about 63% of its correct value, more than 99% after 5τ ≈ 100 million years.

Why to fret about million years, the values are for the test bench.

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LvW said:
pekachoo007, is the max. gain of 40 dB the value you have expected?

Around 70.

LvW said:
Why a dc voltage of 1.1 V ?

What it should be then.

LvW · Oct 14, 2015

pekachoo007 said:
What it should be then.

You have decided to apply a dc voltage of 1,.1 volts - and my question was "why this value" or "for what purpose"?
Applying a certain voltage should serve a certain purpose.

FvM · Oct 14, 2015

Why a dc voltage of 1.1 V ?

A single supply OP should have an input bias within it's common mode range. Hopefully 1.1 V is.

pekachoo007 · Oct 14, 2015

LvW said:
Applying a certain voltage should serve a certain purpose.

The purpose might be certain, with the certainity principle lying somewhere.

LvW · Oct 15, 2015

pekachoo007 said:
The purpose might be certain, with the certainity principle lying somewhere.

So - you dont know why?
This is not a big problem - however, in this case you simply should ask instead of (blindly) using a dc component without knowing its purpose.

pekachoo007 · Oct 15, 2015

LvW said:
So - you dont know why?

might not be

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How to reduce the frequency of its dominant pole

Open loop settings??

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