Open Loop Half Bridge SMPS really needs SiC FETs

No idea what you think this simulation is demonstrating. It's completely different from the previous design. Also not sure why you added the external leakage inductor, normally that is only done for a PSFB in order to help with ZVS.

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...thanks, here is the correct sim now. (Standard Full Bridge)
Again, the higher txfmr leakage results in considerably lower dissipation in the secondary diode snubbers. Also, a significantly lower diode pk voltage. {One was with k = 0.98 (20uH=Llk) and the other, k = 0.995 (Llk=5uH)}
Both had i(mag) primary of pkpk = 5.2A
On the primary side, the higher leakage one results in a slightly bigger mosfet dissipation (9.7W vs 8.6W)

try it at the required phase shift for 5% load ....

and tell us how that went .... (?)

you may find that real life ckts behave differently to the sim ... esp 0 - 30% load ....

try it at the required phase shift for 5% load ....

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Thanks yes i will do, i would imagine we will get spikes due to the sudden discharge of our Cds caps, when at light load.........As you know, it would need looking in to to see how significant a problem this was.

Also, These two LTspice attached sims (attached here) also show the “Rule of SMPS” quite well. Both are Half Bridge SMPS’s, but one uses a large transformer leakage inductance, and the other has a signficantly lower transformer leakage L.

It demonstrates again that high leakage inductance in the transformer in Bridge SMPS’s leads to severe reverse recovery problems in the primary side transistors....running the sim shows severe reverse recovery in the one with high transformer leakage....but not in the other sim with low leakage.

This is also noted in the PSFB, where the transformer is always designed to be tightly coupled, and the leakage inductor is designed to be external to the transformer…..with diodes to the rails to freewheel the dreaded leakage inductor current flow.

It really does appear to be the case, (the aforementioned "Rule of SMPS"), that if doing an offline Bridge type SMPS with a relatively high leakage term in the transformer, then SiC FETs are needed....or alternatively, very heavily damped gate drive and low switching frequency....though i would say thats chancing it, and the SiC FETs are best.

Actually, what about the attached as a means of doing a Half Bridge with no reverse recovery in the primary?.....no marks for effiency, but surely a worker......any gremlins in this?

leakage is only a problem when there is no path for the current at fet turn off - for 1/2 bridge and full bridge there is always a path

much more of an issue for o/p diodes where - once REVERSE recovery current starts to flow - there is no path when the diode finally decides to actually go to OFF.

Turning on a fet when its partner in a totem pole is carrying diode current is generally a bad idea - unless you do it in a controlled and thoughtful manner ...

Turning on a fet when its partner in a totem pole is carrying diode current is generally a bad idea - unless you do it in a controlled and thoughtful manner ...

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Thanks, as you know, its being sure that you never do it under whatever circumstance, no matter how rare.
As we know, Post #9 tells of some of the ills.

however, your comments on leakage inductance imply that this is exactly the operation you envisage, which can happen for too short dead times ...

Thanks, yes i agree, too short dead times........i believe we can do a controller which will totally avoid that ever happening, but as you know, even this step wont alleviate totally the problem of reverse recovery in primary FETs.

It will unless Llk is very large ...

It will unless Llk is very large ...

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Thanks, the attached half bridge smps uses the leakage inductance instead of an output inductor and has LP=2.2mH and Llk = 109uH, and we would wonder whether or not that is very large?