Hi,
Here's an old favourite not seen for a while...an open loop Half Bridge SMPS. (Vout 42-62V), Max power 833W.
Looking at 107us on the LTspice, due to these kind of shoot through events, would you agree this converter is best done with SiC FETs?
The shoot through is caused by the high leakage L.....causing current flow in the lower FET's intrinsic diode...then the top FET turns on, with the massive shoot through current, which could indeed kill the FETs.
(PDF schem and LTspice sim attached)
There seems to be a lot more wrong with the circuit than leakage inductance or shoot through current. For example, if the k of the transformer is set to 1, then you don't see shoot through, but you do still see enormous current spikes in the FETs. Are you sure you didn't forget an output choke?
The current spikes are clearly related to substrate diode reverse recovery, I must confess that I don't understand the rather chaotic switching pattern that promotes diode conduction.
If you can't avoid hard reverse recovery, you either need transistors with faster diodes or must slow down turn-on.
There seems to be a lot more wrong with the circuit than leakage inductance or shoot through current. For example, if the k of the transformer is set to 1, then you don't see shoot through, but you do still see enormous current spikes in the FETs. Are you sure you didn't forget an output choke?
.......thanks, thats exactly what i thought when i saw this. But i can assure, there is no output choke. There must be deliberate leakage inductance. Ive tested and probed this product with a DMM at the customers premises, they wouldnt let me take a scope to it.
Thanks.......that is a great observation, and what i was suspecting also.....i think we can even make a "Rule of SMPS" here...and state that any Transformer isolated , bridge type SMPS, if having much leakage inductance, then it is in danger of suffering severe reverse recovery due to a Leg FET turning ON when the other Leg FET's diode is conducting........we know that this is always an imminent problem in the PSFB and the LLC....but now we can extend our fears to hard switching , bridge type, transformer isolated SMPS's that have significant leakage inductance.
I believe this is the first time such a "rule" has been postulated?...you saw it here first!
...Correct me if im wrong, but I believe that the above quote is referring to the danger of severe reverse recovery brought on by use of high leakage inductance in a standard full bridge SMPS?
..The thing is, at the customer premises, i have before me, a 850W Half Bridge SMPS, (100-265vac in, 42 vout) with no output inductor, and high leakage inductance (its open loop too, at max duty cycle when on full load)........i am telling them its unwise....and they are telling me.....nonsense, this thing has been in the field in use for over 10 years in large numbers, and its fine...the failure rate is very low, and very acceptable.
......However, i believe that they have luckily managed with it because they have a fairly weak gate drive.....which uses weak 2N2222/2N2907 totem poles and a fair bit of series resistance.......this means that FET turn ON is so slow, that its able to survive the reverse recovery events when they happen. The FETs incidentally, are IRFP460A, whose intrinsic diode has a trr of 460ns !!!
The cynical side of me says that this is an SMPS designed such that it can't readily be copied.....in other words, some of the 2N2222/2N2907 totem poles probably do switch fast, due to the BJTs being high tolerance hfe......and these probably blow up during extensive soak and transient testing post-production...but those units that die, are just rejected. The place where these are designed/built, probably has loads of cheap_wage staff on hand to carry out such extensive testing.
I modified a few things, including adding an output choke. Now there's no shoot through current regardless of the leakage (though behavior is better overall with some leakage, helps the FETs soft switch). So no, the FETs aren't inherently a problem if used correctly.
I modified a few things, including adding an output choke. Now there's no shoot through current regardless of the leakage (though behavior is better overall with some leakage, helps the FETs soft switch). So no, the FETs aren't inherently a problem if used correctly.
Thanks, but i am not speaking of "shoot through current"......that is where both leg fets are ON at the same time...i am speaking of one leg FET being turned ON, when the other leg FETs diode is in conduction.
By the way, i am sure you know, the severe reverse recovery only happens in severe transients, such as non-soft start and sudden no-load to full-load and vice versa, so that is how it is needed to be simulated.....not just steady max load...in steady max load there is no problem...i am sure you appreciate this.
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I modified a few things, including adding an output choke. Now there's no shoot through current regardless of the leakage (though behavior is better overall with some leakage, helps the FETs soft switch). So no, the FETs aren't inherently a problem if used correctly.
Thansk, i actually no-loaded your sim and noted that it sees severly high shoot through at startup on noload, as attached....and that was with zero Leakage L.........so there is a bit more to the "Rule of SMPS" above i now confess
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...blast sorry, i meant to say "severely high reverse recovery current spike" rather than "shoot-through".
By the way, i am sure you know, the severe reverse recovery only happens in severe transients, such as non-soft start and sudden no-load to full-load and vice versa, so that is how it is needed to be simulated.....not just steady max load...in steady max load there is no problem...i am sure you appreciate this.
Thansk, i actually no-loaded your sim and noted that it sees severly high shoot through at startup on noload, as attached....and that was with zero Leakage L.........so there is a bit more to the "Rule of SMPS" above i now confess
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...blast sorry, i meant to say "severely high reverse recovery current spike" rather than "shoot-through".
Sure, running the sim at no load produces some awful transients (especially on the C1/C2 divider). This can cause the FET body diodes to conduct, which therefore brings up issues with reverse recovery. Usually the best way to resolve this is through a soft-start, or by damping things with feedback.
Your original assertion was that SiC FETs are "needed" for this. Well, if you insist on applying unnecessarily stressful transients to the circuit, then yeah perhaps SiC FETs would help. But they're not necessary if you just design and control the rest of the circuit properly.
Wide bandgap semiconductors aren't meant to be a substitute for common sense.
Sure, running the sim at no load produces some awful transients (especially on the C1/C2 divider). This can cause the FET body diodes to conduct, which therefore brings up issues with reverse recovery. Usually the best way to resolve this is through a soft-start, or by damping things with feedback.
Your original assertion was that SiC FETs are "needed" for this. Well, if you insist on applying unnecessarily stressful transients to the circuit, then yeah perhaps SiC FETs would help. But they're not necessary if you just design and control the rest of the circuit properly.
Thanks, these are excellent points. -And as you know, bring up further considerations as follows....
The Converter of the top post is what we are evaluating for purchase from an external. It comprises the shown open loop Half Bridge SMPS with output power 833W, (as in top post sim). This converter uses the L5991 Controller with a 1nF soft start cap...therefore it has a nearly non existent soft_start of 269us to 500us (350us nominal). It also has no feedback loop... just a primary overcurrent limiter. However, we are told , with some evidence, that it is highly sucessful, with the great majority of units lasting >10 yrs in the field.
Given the extremely valid conclusions of post #8 above, how do we then believe this?
Usually the best way to resolve this is through a soft-start, or by damping things with feedback.
...Thanks, as discussed, the converter we are evaluating has no feedback loop, and pretty well no soft_start....yet it is sucessful in the field, this is what we are told.
As you know, even if this converter did have a decent soft start....there are input power disturbances which can bring about non-soft-restarts, when for example the soft start capacitor stays charged up as a new re-start begins.
Also, even if this converter did have a feedback loop, then as you know, there are power system disturbances which can saturate the feedback error amplifier output...rendering the feedback loop non operative, for long enough for a transient to cause whatever mayhem as has been discussed in this thread.
......As such, i am still not convinced that for the converter in the top post, a SiC FET solution is not adviseable...in other words , it really needs SiC FETs. The unit we are being shown does not actually use SiC FETs...though i discuss why i believe this converter is getting away with it (not using SiC FETs) in post #5 above (bottom bit about the potentially weak FET gate drives).
Apologies Mtwieg if i possibly straw-manned you a bit there...i was trying to keep my word count down and hope i didnt abbreviate things too much.
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Anyway, i think the "Rule of SMPS" of post #5 above needs some modification if you agree...
The "Rule" speaks of hard-switched Bridge Type SMPS's with relatively large leakage inductance. The thing is, i think that's only part of the story..... After all, a "normal" Full Bridge SMPS using an ungapped transformer core, may well have a primary inductance of 10mH or so. Then, even with a tight pri/sec coupling of k = 0.995, the leakage inductance could be as high as 100uH....and yet, in a standard hard switched Full bridge SMPS, with that kind of leakage inductance, we wouldn't expect to have to deal with severe reverse recovery problems in the primary side of the bridge......So i actually believe that the "doom" is caused by a combination of relatively high leakage inductance and relatively high magnetising current acting together....And even then, the "doom" is only instigated by the action of severe load/line transients including startup and non_soft_restart_up, and also sudden overloads.
If you examine the converter of the top post, then it has relatively high magnetising current (partly due to Lp= 1.2mH), and relatively high leakage inductance (40uH). It is the combination of these two, coupled with transients, that excites the severe reverse recovery in the primary side of the Bridge...(given the 'injection' of transients in to the fray).
......This kind of makes sense, because the Phase Shift Full Bridge, also has relatively high primary referred magnetising current, and relatively high primary "leakage" inductance (even if by way of an external "leakage" inductor)...and we all know that the Phase Shift Full Bridge, potentially has horrendous primary side reverse recovery problems if not dealt with properly.....of all the fairly commonly used converters, the Phase Shift Full Bridge is the potentially the most venomous of all......as follows....
....So when we consider the "Hard Switched , Standard Full Bridge SMPS with high leakage inductance, and high magnetising current", we have a converter which suffers the same problems as the Phase Shift Full Bridge, in relation to severe reverse recovery problems in the primary side.
Thanks, may i please ask, was that in relation to the PSFB, or standard Full Bridge, or Open loop Full bridge> ( ie OLFB of the top post)...sorry, but the thread has bounced about a bit more than expected.
Thanks,, sorry to ask again, please dont answer if not time, you've been way too good as it is....but what would you say was "modestly low leakage inductance".....or does it depend?...
For example, the Open Loop Full Bridge of the top post of this thread has primary leakage inductance of 40uH (LP=1.2mH). Would you say that was too much in your recomendation?......ie, is 40uH so high that we will suffer from severe reverse recovery in the primary side following certain transients?
Also, what about a standard full bridge which is not sandwich wound, (and doesnt have a gapped core) and has an LP of 10mH, and a k factor of 0.99, and thus a leakage inductance of 200uH?...is that too high...or again, does it depend?...eg depend on the magnetising current that will flow?
leakage inductance should be considered in light of the current to be switched and the freq,
for example if turning off 10A with 10uH Llk @ 100kHz - this is 50 watts that needs to go somewhere ( snubbers or ringing in parasitic R of wdgs and circuit )
1uH gets it down to 5 watts, and dropping to 50kHz gets it down to 2.5 watts ( per mosfet )
High leakage can be tolerated somwhat ( not good for o/p diodes ) in Ph sh full bridge - but not really in standard 1/2 or full bridge where you just need huge snubbers to overcome ...
We routinely design transformers 1kW < Tx < 5kW that have leakages less than 0.25 % ( of Lp ) - and some others will considerably less than that
High leakage can be tolerated somwhat ( not good for o/p diodes ) in Ph sh full bridge - but not really in standard 1/2 or full bridge where you just need huge snubbers to overcome ...
Thanks, this is very interesting for us, since we are being offered to buy the Open Loop Full Bridge of the top post of this thread. Its 42Vout, 833Wout. It has Lp=1.2mH. As can be seen, it has a 40uH leakage inductance (primary). It actually uses that as its "output inductor" and has no secodnary side output inductor.
Its output diodes have no snubbers. The only snubber is the two P6KE91CA Bidi TVS's on each of the split sec coils. P6KE91CA is just 6.8mm by 2.6mm. Its a very small snubber for an 833W Full Bridge. So from this, it seems that not much snubbing is needed to counteract relatively large primary leakage L in Full Bridge?......This PSU is said to have v low fail rate and majority of units do >10 years in service.
Thanks, this is very interesting for us, since we are being offered to buy the Open Loop Full Bridge of the top post of this thread. Its 42Vout, 833Wout. It has Lp=1.2mH. As can be seen, it has a 40uH leakage inductance (primary). It actually uses that as its "output inductor" and has no secodnary side output inductor.
Using the leakage as a substitute for a proper output choke is an extremely poor decision IMO (except for cases like LLC of course). That means your FETs are going to carry the freewheeling current, which is why you're more likely to see horrible reverse recovery issues. Transformer leakage inductance itself is going to be much lossier than a proper choke as well. Using a discrete "leakage" inductor would mitigate that, but then what is the point...
The attached Full Bridge SMPS simulation (in LTspice) in fact shows, that power dissipation in secondary diode snubbers does not increase when leakage inductance increases in the Full Bridge transformer. (Running it with k = 0.995 then k = 0.98)
...PDF of schem also shown
...the FET power dissipation is a tiny bit more with more leakage.
However, I still believe that when combined with a significant amount of i(mag), then the larger Leakage inductance can lead to the severe reverse recovery in primary side following certain transients.
If you run open loop - you can set the dead time to account for the time the current takes to decay in the o/p diodes due to the (AC not DC ) inductance seen at the Tx output due to leakage, this allows near full pwm with little effect on the o/p diodes ( you can also have extra C across the mosfets to slow the transition across the o/p diodes which helps too ). As the pri side needs to be soft switched the extra leakage in the Tx helps to get this over a wide load range ( i.e. down to zero load ) and the dead time can be set to just achieve this ( i.e. ZVS at zero load ).
Start up can be an issue with the above set-up - usually a soft pwm start is needed and the fets and diodes take the heat ( current and volt spikes ) during start.
this is likely why the TVS's are placed across the sec - to stop the diodes blowing up due to over-volts at start.
However - all the nice effects of open loop disappear the moment you try to achieve pwm control .....
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Also while the dead time may save you from flux drift in the Tx under "normal" operation - it may not always be the case under start up or for transient loads - unless the Tx is over designed, e.g. 150mT max on a core that can go to 350mT or higher worst case
The attached Full Bridge SMPS simulation (in LTspice) in fact shows, that power dissipation in secondary diode snubbers does not increase when leakage inductance increases in the Full Bridge transformer. (Running it with k = 0.995 then k = 0.98)
No idea what you think this simulation is demonstrating. It's completely different from the previous design. Also not sure why you added the external leakage inductor, normally that is only done for a PSFB in order to help with ZVS.
No idea what you think this simulation is demonstrating. It's completely different from the previous design. Also not sure why you added the external leakage inductor, normally that is only done for a PSFB in order to help with ZVS.
Blast, sorry about that , well spotted, i pulled it from my files and didnt see the diodes to rail or external leakage inductor......but anyway, it still demo's the situation with relatvely high leakage inductance, and relatively high magnetising inductance....and that a Full bridge like that would be just as bad as a PSFB. Also, it demo's that the primary side leakage inductance , when increased, doesnt result in extra dissipation in the secondary diode snubbers.