melkord
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I have been trying to understand this for quite sometimes.
1. Why is the -3dB cutoff freq of the folded cascode that I simulate too low?
2. Which configuration is the correct one to simulate the openloop gain and phase margin?
I use open loop configuration like in the pic below.
All the MOSFET are in saturation
I take a look at this discussion, but I still do not get it.
As discussed in that thread, we do not involve or consider -3dB freq during designing, we just consider UGB.
On page 49 of this slide, the openloop configuration is different.
On Baker, there is some feedback, but it is still said openloop. Ch24 Fig24.43.
1. Why is the -3dB cutoff freq of the folded cascode that I simulate too low?
2. Which configuration is the correct one to simulate the openloop gain and phase margin?
I use open loop configuration like in the pic below.
All the MOSFET are in saturation
I take a look at this discussion, but I still do not get it.
As discussed in that thread, we do not involve or consider -3dB freq during designing, we just consider UGB.
On page 49 of this slide, the openloop configuration is different.
On Baker, there is some feedback, but it is still said openloop. Ch24 Fig24.43.
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