sherazi
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They are shown - and single supply, because both OPs shares the supply pins.Why don't you show us the power supply (supplies?) for the 1st stage? It is important to know if single or double supply!
The latching behaviour is caused by the positive feedback, as said. The first stage, if the real circuit is wired according to the schematic, has a low output voltage in idle state.and the problem is in first stage as its output stays high even when the i/p is low again.
but when a new pulse comes its ok again.
the problem i am facing is that some times the O/p LED wont stop glowing after a pulse is low again .its not always like this but still quite a few times and after another pulse the led will go off after the pulse is finished ...
They are shown - and single supply, because both OPs shares the supply pins.
It's clear, if you have the LM358 pin assignment in mind.Hard to detect.
According to the common mode range of LM358, it will work as a half-wave rectifier with gain. Depending on the individual LM358 offset voltage, low level signals may be suppressed. Although this operation mode isn't reasonable at all, the first stage still passes an input signal.I doubt how the 1st stage will find a proper bias point.
It's a good point to consider possible latch-up. According to the datasheet, it can be excluded for the present circuit however. It specifies a maximum clamp diode current of 50 mA and states about the expectable behaviour in note 3:When I use LM358, I try not to let its input go below 300mV (to have a good margin before a possible latch up). In this circuit, L2 via C5 may drive the positive input below 700mV at which the output may be undetermined or be latched to a high state.
In other words, polarity reversal can be expected, latch-up shouldn't happen. The AC coupling prevents larger clamp current even in the case of higher input voltages. In the present case, the moving magnet won't hardly be able to supply it, however.This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors
becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltages of the op amps to go to the V+voltage level (or to ground for a large overdrive) for the time duration that
an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value
greater than −0.3V
Don't what it is or what it's good for.i have tried using a Rc compensating resistor at noninverting input
iN the second stage VR is 4.5Mohm used for sensitivity selection , its in feedback loop if the input of second stage is less than 2.5V the output is low ,if it becomes higher then the o/p is high
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