opamp open-loop post-simulation

[presun]

Hello, I have a few questions regarding op-amp post simulation.

1. When performing an open-loop post simulation of an op-amp, is it normal for the results to be incorrect? I have tried multiple times, but the biasing seems to be off, and the values do not come out correctly. (In closed-loop simulations, the post simulation results appear fine.)
2. When placing NMOS and PMOS transistors in the layout, is it beneficial to keep the spacing as tight as possible?
3. When applying a guard ring around NMOS transistors, is it better to increase the spacing between NMOS and PMOS transistors so that dummy structures can contact all four sides of the guard ring?
4. When adding a bypass capacitor next to a DC BIAS pad, what is the typical value used?

 

[FvM]

Not clear how you set up open loop simulation. In any case, it requires a means to achieve correct bias.

 

[presun]

Not clear how you set up open loop simulation. In any case, it requires a means to achieve correct bias.

I conducted a simulation in the opamp in the picture below.
I have also attached a picture that I have added feedback on.

 

[sidun.av]

When performing an open-loop post simulation of an op-amp, is it normal for the results to be incorrect? I have tried multiple times, but the biasing seems to be off, and the values do not come out correctly. (In closed-loop simulations, the post simulation results appear fine.)

Again, it depends on the results you get and what you call "normal".
Bias voltages are a few mV off - fine. Bias currents are a few % off -fine. DC Gain/BW/PM changed a bit - fine. But if your transistors are out of the operation region, bias voltages/currents are changed significantly or DC gain/BW/PM are changed - something is definitely wrong. Until we see exactly what parameters changed and how what testbench did you use and what your concern is - it's really hard to help you.

When placing NMOS and PMOS transistors in the layout, is it beneficial to keep the spacing as tight as possible?

Are you talking about the spacing from [NMOS to NMOS, PMOS to PMOS] or [PMOS to NMOS]?
For the first case - it's beneficial to abut them, just a tighter spacing doesn't really change anything. You can read more about these effects here:

Matching in layout - AnalogHub

This article describes matching techniques in layout, matching patterns and design impact

analoghub.ie

When applying a guard ring around NMOS transistors, is it better to increase the spacing between NMOS and PMOS transistors so that dummy structures can contact all four sides of the guard ring?

I don't understand your question. What do you mean by dummies can contact four sides of the guard ring? Can you draw a picture or show us in layout what exactly do you mean? Speaking about dummies - you can find more information here:
https://analoghub.ie/category/Layout/article/layoutMatching (Dummies section)

When adding a bypass capacitor next to a DC BIAS pad, what is the typical value used?

It depends on the application. You can calculate the required value based on the BW.

--- Updated Feb 5, 2025 ---

I conducted a simulation in the opamp in the picture below.
I have also attached a picture that I have added feedback on.

What simulation are you performing in open-loop? Is it AC/DC/Tran? What are the test conditions and what do you expect? What didn't match your expectations?

 

[presun]

다시 말해서, 이는 얻는 결과와 무엇이 "정상"인지에 따라 달라집니다.
바이어스 전압이 몇 mV 틀렸어도 괜찮습니다. 바이어스 전류가 몇 % 틀렸어도 괜찮습니다. DC 이득/BW/PM이 약간 변경되었어도 괜찮습니다. 하지만 트랜지스터가 작동 영역을 벗어나거나, 바이어스 전압/전류가 크게 변경되었거나, DC 이득/BW/PM이 변경되었다면 확실히 문제가 있습니다. 어떤 매개변수가 변경되었는지, 어떤 테스트 벤치를 사용했는지, 그리고 우려 사항이 무엇인지 정확히 알 때까지는 도움을 드리기 어렵습니다.


[NMOS 대 NMOS, PMOS 대 PMOS] 또는 [PMOS 대 NMOS] 간격에 대해 말씀하시는 건가요?
첫 번째 사례의 경우 - 인접하는 것이 유익합니다. 간격을 좁히는 것만으로는 실제로 아무것도 바뀌지 않습니다. 이러한 효과에 대한 자세한 내용은 여기에서 읽을 수 있습니다.

https://analoghub.ie/category/레이아웃/기사/레이아웃매칭

질문을 이해하지 못하겠어요. 더미가 가드 링의 네 면에 접촉할 수 있다는 건 무슨 뜻인가요? 그림을 그리거나 레이아웃으로 보여줄 수 있나요? 더미에 대해 말씀드리자면, 자세한 내용은 여기에서 찾을 수 있습니다:
https://analoghub.ie/category/Layout/article/layoutMatching (Dummies 섹션)


응용 프로그램에 따라 다릅니다. BW를 기준으로 필요한 값을 계산할 수 있습니다.
[자동병합]1738749599[/자동병합]

오픈 루프에서 어떤 시뮬레이션을 하고 있나요? AC/DC/Tran인가요? 테스트 조건은 무엇이고 무엇을 기대하시나요? 기대에 부응하지 못한 점은 무엇인가요?

The current problem is that the bias is not properly caught in the second stage and does not work.
Originally, the output dc voltage was designed to be 950mV, but post simulation showed 200mV, which causes the nmos to go to the triode area. Of course, the bias stabilizes when the feedback is connected, but I was wondering whether it is desirable for the result value to be similar to pre-sim even in open-loop, or whether post simulation in open-loop in general has low bias.

 

[sidun.av]

The current problem is that the bias is not properly caught in the second stage and does not work.
Originally, the output dc voltage was designed to be 950mV, but post simulation showed 200mV, which causes the nmos to go to the triode area. Of course, the bias stabilizes when the feedback is connected, but I was wondering whether it is desirable for the result value to be similar to pre-sim even in open-loop, or whether post simulation in open-loop in general has low bias.

What NMOS you are talking about? M50? It looks like it has a fixed voltage VB, how can it be "stabilized" by the feedback?
Your output voltage has to be 950mV at what condition at the input? Did you check your opamp performance in AC and tran?
Once again, please provide clear information on your test setup, analysis and changes.

 

[presun]

What NMOS you are talking about? M50? It looks like it has a fixed voltage VB, how can it be "stabilized" by the feedback?
Your output voltage has to be 950mV at what condition at the input? Did you check your opamp performance in AC and tran?
Once again, please provide clear information on your test setup, analysis and changes.

That's right. It's M50. The voltages were adjusted to the node voltages intended by pre-simulation by feedback.
I don't know the exact reason yet.
The input signal is vin,dc=950 mV, and the AC signal enters the VINN. Only the dc voltage is applied to the VINP.
VB = 700 mV.
When post-simulation was conducted by feedback (op-amp is used for post-simulation, feedback resistance is used for analoglib) it was confirmed that the op-amp performance came out well in ac and tran.
(Intended closed-loop gain=40dB)

 

[sidun.av]

The voltages were adjusted to the node voltages intended by pre-simulation by feedback.

I didn't get this. Isn't your VB fixed?

The input signal is vin,dc=950 mV, and the AC signal enters the VINN. Only the dc voltage is applied to the VINP.
VB = 700 mV.

Can you show us the waveforms and calculations of the expected result?

When post-simulation was conducted by feedback (op-amp is used for post-simulation, feedback resistance is used for analoglib) it was confirmed that the op-amp performance came out well in ac and tran.

Did you check across PVT? Did you check the operating points of your devices during these tests?

 

[BradtheRad]

You probably desire zero output for zero input. Since time immemorial, advice is to give op amps a bipolar supply. Hence adjust VSS into negative polarity so that you get 0V on the wire labelled VIN1. That is when your long-tail pair can work as a differential detector.

Then somewhere in your output stage you want high gain. High gain should be available toward either polarity in response to small bias in either direction. Yet we also hope to avoid shoot-through. That's the reason for the baffling array of transistors in the middle of an op amp.

Even then the output tends to drift uncontrollably toward either positive or negative supply rail and stay there. By installing the (opposing) feedback signal you achieve zero output for zero input.

 

[dick_freebird]

I prefer to set up a closed loop simulation in an
application-reasonable negative feedback gain,
and then break the AC feedback with a 1 Henry
inductor.

I despise the Cadence "iprobe", it's a lying liar
whenever it feels like it (like the 41st MC iteration
and now you get extra fun 'splaining your zero
gain "sports" in the distribution).

I "sniff" the real time input difference voltage
with a vcvs A=1, and my gain & phase are then
the same simple arithmetic you'd normally use.
This is also amenable to fully differential op amp
with another vcvs at the outputs.