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OPAMP offset in the pipelined ADC, Thanks!!

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frozenduck

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opamp offset adc

In the tranditional pipelined ADC, the maximum output occurs when 2*vin-vref+ vos_opamp where vin=vref. If we say the opamp offset is 10mV(because of mismatch in opamp) and vin is 500mV. VDD=1.2V.

The hightest output of MDAC1 will be 2*500m-500m+10mV=510mV.

This 510mV will be digitized by the following stages and the output of MDAC2 will be 2*510m-500m+10mV=530mV

We can find the output voltage is already out of range and causes distortion. It will also saturate the opamp at the last few stages because the offset in the previous stages will be amplified.

I find there are two ways to deal with it.

1. auto-zero technique
The opamp should be connected in unity gain when sampling. However, vincm may not equal to vocm and I rarely see it in papers talking about pipelined ADC without digital calibration.

2. use vin smaller than vref to have some margin.
However, this may not be useful because 10mV offset in the first stage will be 10mV*2^8 in the 8th stage.


Can anyone give me some advices?
Thanks.
 

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