opamp of Pipeline ADC latter stages

[iamxo]

pipeline adc

As we all know, in pipeline ADC the capacitor size could be scaled down in latter stages together with the opamp current ( however the GBW should be constant).

However, when i was designing the opamp for MDAC(which is used in latter stages, that is to say small cap could be used), i found that i need large current to maintain the closed-loop GBW, because the parasitic cap at the gate of input transistor is large enough to be comparable to the caps in MDAC, which leads to small feedback factor and results in small closed-loop GBW. it degrades the settling of the closed opamp.

So, does anybody face the same problem? How did you solve it? thank you all~

 

[eecs4ever]

decrease parasitic cap

Maybe you should scale the size of your Op-amp too?

for example: if you scale the capacitors by 4, and the op amp by 4, your feed back factor will be approximately the same instead of getting smaller. So then currents can be scaled down too.

 

[iamxo]

op amp ft

Suppose the capacitor value is as this: Cs = 0.25p, Cf = 0.25p, Cload = 0.25p
and the opamp input parasitic cap is Cp = 0.2p, then the feedback factor is only
0.25/(0.25 + 0.25 + 0.2) = 0.357, so if i want the closed-loop GBW to be 900M, then my opamp open-loop GBW should be 900M/0.357 = 2.52G.

However, since the input parasitic cap is fixed, the size of input transistor is also fixed. if i need such high GBW (2.52G), what i can do is to increase the current.

so, is this right? or i choose too large load cap for the next stage (here 0.25p, that is 0.125p for sampling and another 0.125p for feedback).
Thank you all.

 

[eecs4ever]

op amp gbw vs ft

"However, since the input parasitic cap is fixed, the size of input transistor is also fixed. if i need such high GBW (2.52G), what i can do is to increase the current. "

Why are the input transistor's size fixed? Maybe you should scale them down.

 

[iamxo]

i have already scaled it, the input parasitic cap in former stages is larger, almost 1p in the first stage.

 

[eecs4ever]

"As we all know, in pipeline ADC the capacitor size could be scaled down in latter stages together with the opamp current ( however the GBW should be constant). "

Is your question about scaling ?

the feedback factor , f = Cf/(Cf+Cs+Cp) , when you scale everything by a factor K, f remains the same.

 

[iamxo]

"As we all know, in pipeline ADC the capacitor size could be scaled down in latter stages together with the opamp current ( however the GBW should be constant). "

Is your question about scaling ?

the feedback factor , f = Cf/(Cf+Cs+Cp) , when you scale everything by a factor K, f remains the same.

uh, it sounds reasonable, however, we need to maintain the opamp GBW, so the Cp is not scaled the same as Cs or Cf. In a word, my problem is that i can not use low current to achieve high closed-loop GBW mainly due to large input parasitic cap. I do not know how to solve it.

 

[timof]

uh, it sounds reasonable, however, we need to maintain the opamp GBW, so the Cp is not scaled the same as Cs or Cf. In a word, my problem is that i can not use low current to achieve high closed-loop GBW mainly due to large input parasitic cap. I do not know how to solve it.

Can you change the metal routing in order to decrease parasitic capacitances?

 

[iamxo]

uh, it sounds reasonable, however, we need to maintain the opamp GBW, so the Cp is not scaled the same as Cs or Cf. In a word, my problem is that i can not use low current to achieve high closed-loop GBW mainly due to large input parasitic cap. I do not know how to solve it.

Can you change the metal routing in order to decrease parasitic capacitances?

this parasitic cap is the gate cap of input transistor not the layout parasitic cap, it can not be reduced if using large transistors.

 

[Usman Hai]

iamxo, I think you are missing very important point here. ft of an opamp can be given as ft=β gm/Cl. When you scale the stages, the load feedback factor remain constant however, the load capacitance is reduced half (assuming you scaling down by 2 approx and not taking into account unscaled parasitics like CMFB etc etc ). So, when Cl is halved, you need half the current to keep the same gm and half the input transistors to keep the same current density (or Vdsat). Therefore, later stages opamp must use half the current.

In one of my papers (which is about to publish soon) I derived the relationship between the ft, Cl and Cip(input parasitics) as well in to make the designing of later stages more systematic. I can send you the paper once it will be published. I can tell you that there is an optimal size for input cap to get the max efficiency and minimum power. In other words if your input parasitics are more or less than that optimal value, you will be burning more power to get the desired ft.

 

[iamxo]

iamxo, I think you are missing very important point here. ft of an opamp can be given as ft=β gm/Cl. When you scale the stages, the load feedback factor remain constant however, the load capacitance is reduced half (assuming you scaling down by 2 approx and not taking into account unscaled parasitics like CMFB etc etc ). So, when Cl is halved, you need half the current to keep the same gm and half the input transistors to keep the same current density (or Vdsat). Therefore, later stages opamp must use half the current.

In one of my papers (which is about to publish soon) I derived the relationship between the ft, Cl and Cip(input parasitics) as well in to make the designing of later stages more systematic. I can send you the paper once it will be published. I can tell you that there is an optimal size for input cap to get the max efficiency and minimum power. In other words if your input parasitics are more or less than that optimal value, you will be burning more power to get the desired ft.

Thanks hai, i know the optimum value relationship from one jssc paper which briefly described it(but i think there is error in the paper's description or maybe i misunderstood), So i will expect your detailed explaination from your paper.

the paper is titled: "A 55-mW 10-bit 40-Ms/s Nyquist-rate CMOS ADC" jssc 2000, in the appendix

 

[PaloAlto]

In one of my papers (which is about to publish soon) I derived the relationship between the ft, Cl and Cip(input parasitics) as well in to make the designing of later stages more systematic. I can send you the paper once it will be published...

I'd love to see that paper. Can you send it to me once it's ready? Just reply here, or as pm and I can give you my email

 

[kazu_kazu]

In one of my papers (which is about to publish soon) I derived the relationship between the ft, Cl and Cip(input parasitics) as well in to make the designing of later stages more systematic. I can send you the paper once it will be published...

I'd love to see that paper. Can you send it to me once it's ready? Just reply here, or as pm and I can give you my email

Dear Mr Usman,

would you mind letting me to see your paper too?
I'm designing 12 bit pipelineADC for my final project
and I found the same problem..

thank you in advance..

kazu

 

[Usman Hai]

Its here
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5338964&isnumber=5338937

However its a conference paper, so many details not given.
/Noman Hai

 

[kazu_kazu]

actually will scalled down the op amp
fix linearity problem?

because my most problem is the linearity..
I only get 29dB for SFDR..

thank you in advance

 

[Usman Hai]

Increase the opamp gain and let it settle completely. It should solve your linearity issue.