OPAMP in BGR

nitishn5 said:

You have two loops in your BGR.

Opamp- to M3_gate to M3_drain to Opamp-
And
Opamp+ to M4_gate to M4_drain to Opamp+

One of them is a positive feedback loop and the other is a negative feedback loop.

You want your negative feedback loop to have more gain than the positive feedback loop and that happens by design in the above schematic.
Now if you flip the opamp inputs, then you have got more gain in the positive feedback loop. and hence your BGR is dead.

Also, you need to check the stability in-situ. That is, with the opamp as part of the loop.
Your negative feedback loop mentioned above needs to be stable. Not just the opamp alone.

Click to expand...

It was very helpful!

So (-) is higher than (+) on turning,
since their potential difference is Vt*lnN for initial condition

I need to test its stability then

What are the missing assumptions? Can it work without these?

Won't AV+ always be greater than AV- since AV+ = 1 + AV- right "?
Thus V/2 with 2 R's are needed for feedback to Vin+ to make this Bandgap work !!

Was this out of Saleh Razini's textbook? It fails.

Without an explicit startup circuit there's always some probability it won't. Check for op amp input null and output pulling sane current to see if loop is closed.

You probably prefer an OTA as the output of interest is a current
and excess current, in some topologies, can kick you to a third, latched state.

AS is , the Op Amp will saturate with excess Av+=1+|Av-|

I tried another idea. Loading the negative feedback to Vin+ to ground. That seems to work. But needs an OTA out for load regulation as @dick_freebird said.

SIM> https://tinyurl.com/22rq6y3b

dick_freebird said:

Without an explicit startup circuit there's always some probability it won't. Check for op amp input null and output pulling sane current to see if loop is closed.

You probably prefer an OTA as the output of interest is a current
and excess current, in some topologies, can kick you to a third, latched state.

Click to expand...

I've made startup circuit, i think it works fine

but I can't understand excess current one
Do you mean additional PMOS (more current mirros) will bring more Capacitors, will make OPAMP unstable?

Without considering saturation, the basic #1 circuit has two stable operation points, I = 0 and I = ln( n)*VT/R1. Startup circuit has to enforce I > 0.
Saturation is a possible issue of the practical current source circuit, but not relevant to analyze principal behavior.

Loop phase margin is another topic. Presume that it can be always achieved by appropriate frequency compensation with dominant pole.

dick_freebird said:

Without an explicit startup circuit there's always some probability it won't. Check for op amp input null and output pulling sane current to see if loop is closed.

You probably prefer an OTA as the output of interest is a current
and excess current, in some topologies, can kick you to a third, latched state.

Click to expand...

I've made startup circuit, i think it works fine

but I can't understand excess current one
Do you mean additional PMOS (more current mirros) will bring more Capacitors,

FvM said:

Without considering saturation, the basic #1 circuit has two stable operation points, I = 0 and I = ln( n)*VT/R1. Startup circuit has to enforce I > 0.
Saturation is a possible issue of the practical current source circuit, but not relevant to analyze principal behavior.

Loop phase margin is another topic. Presume that it can be always achieved by appropriate frequency compensation with dominant pole.

Click to expand...

Thank you sir

Perhaps @dick_freebird can give an example of excess current latching behaviour. I just imagine that it's possible, similar things happen with many circuits.

I first encountered this in the '80s, I inherited
a floundering chip design in a bipolar technology
which used PTAT loops as latches (analog guy
let to do digital design in a "10um node", it
failed, he left, I got my first "non-digital" job
in the linear group - they always let new
interns work the ER, right?).

What I found was that the simple PTAT loop,
comprising two current mirrors with gain and
the usual "corner resistor" had an additional
state besides "off" and "@set-current" - if
driven into saturation of the BJT mirror-
master device (across high-ish natural Rc)
the mirror ratio swings wide and saturates
the other, and now it's a degenerate SCR
more or less, which the wimpy turnoff
switch device could not remove (headroom
low, trying to quench below Vce)sat while the
loop enjoys full supply headroom).

Turned out that the various current mirrors
(in bipolar technology) have different responses
when driven well past designed operating
point.

This attached is an excerpt from a short course
I made, illustrating the mechanism. I took it as
a broader lesson, than any current loop should
be checked out for behaviors beyond lock-in
and any potential to latch (you might find some
triggers in kink / impact ionization "drain curl"
in MOS circuits) and then mitigate. In my BJT
PTAT case, a sufficient value resistor between
the mirrors' legs was enough to return "turnoff
authority" to the reset switch.