opamp design without common mode specifications

[otac123]

hi all,
i am trying to design a two stage opamp with the following specifications
vdd=3v vss=0v ad>50db cl=10pF, o/p swing 2v p-p settling time=100ns.
can a design be done without i/p common mode range???
how do i use settling time in the design?
bye

 

[eng_Semi]

First of all I don't get ur point which says "can a design be done without i/p common mode range???". I get it as follows: you want to design an OPAMP without difficult conditions on the i/p common mode voltage, If this is true so u may try to use OTA folded cascode OPAMP, it has a wide range for i/p common mode levels.

Also I design before an OTA folded cascode which has a gain about 65 dB, with same supply rails. (I get this gain from a single stage)

About the point of settling time, I think it can be measured from the slew rate (I am not very sure from this point)

 

[jiangwp]

From the settling time , the GBW can be deduced.

Then, the compenstation capactance is determined.

From the slew rate, the second bias current and differential bias current are

determined.

From the gain, the input transistor is deterimined.

 

[otac123]

But how do we determine the slew rate from the settling time specifications?
As for the input common mode range which i had said about in the previous post, the problem is that there is no specification given. so what do we assume it as? without the ICMR how can we design the transistors on the input side?
thanks for ur previous replies.... but plz do reply for this.