Opamp DC gain and GBW in Pipeline ADC using the Veriloga model

[rosy65]

Hi all,

I am working on 40Msps 12bit Pipeline ADC 1.5bit/stage. I have to optimize the accuracy and power consumption. My goal is to do the spectral analysis of the output, and the final ENOB and SNR values should be around 12bit and 73dB. I wrote Veriloga models for all the main blocks comparator Preamp and latch, Switch capacitor array and OpAmp. Now I want to sweep the gain and bandwidth of opamp and determine the required parameter metrics of the opamp. I got stuck on how to sweep the values of those. instead of merely sweeping from 50db - 100db or so, is there any way to find the required gain of the opamp for the pipeline adc. I have found like GBW = 1/settling time and the calculated values gain = 66dB and GBW = 0.17GHz. If i am using these values and doing spectral analysis, the ENOB and SNR are around 4bits and 35dB for 2^12 samples. I am not sure where I am doing wrong .

Any leads would be of great help.

Thank you.

 

[dick_freebird]

I think a pipeline ADC is going to care a lot about settling
time (this sets max clock to get the care-abouts like linearity).
This kind of thing is where I expect pretty poor representation
from a behavioral model. AVOL, fine. Small signal GBW, fine.
But pipeline is all transient large signal in operation (trying
to get to a fine outcome).

 

[KlausST]

Hi,

I have to optimize the accuracy

I guess you mean "precision"... like ENOB and SNR.

I´d analyze the data to find out what´s the culprit. Linearity (should result in overtones), noise (should result in random frequencies = noise floor)...

Klaus

 

[rosy65]

i think the issue is with my internal blocks veriloga representation. I have SCOPAMP as a block, which i wrote a model, using pipeline adc transfer functions for residue voltage, mentioned in the figure.

If i have to separate switch cap block and opamp block, how to do that. Because the stage gain is 2, coming from 1+cs/cf, but how to determine opamp gain from this. I am using Laplace veriloga model for opamp.