Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

OPA CMRR simulation methods

Status
Not open for further replies.

cliffj

Member level 3
Member level 3
Joined
Mar 22, 2004
Messages
55
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,288
Activity points
533
Does anyone know better simulation method for the CMRR in an OPA ?

Cliff
 

pspice cmrr

Please refer to "CMOS Analog Circuit Design" by Phillip E. Allen and Douglas R. Holberg.

The simulation circuit can be described in spice as following:

XDUS PLUS MINUS OUT VDD VSS OPAMP
V1 PLUS GND 0 AC 1 0
V2 PLUS OUT 0 AC 1 0
...
.AC DEC ...
.PROBE AC CMRR=VDB(OUT)
 

cmrr opa

hughes,

I am a new entry in analog design.
could you give me some explanations about the spice file above?

thanks!
jordan76
 

cmrr spice

Hi jordan76,

The first three lines define the simulation circuit topology as shown in the figure. The circuit definition for the op amp is not shown here.

Both voltage sources V1 and V2 have a DC value of 0V and AC value of 1V.

The ".AC" statement is a hspice analysis statement. It takes several forms, one of which is as follws:
.AC DEC 10 100 1MEG
This statement will do frequency analysis (AC analysis) from 100Hz to 1 Meg-Hz, taking 10 frequency points for every decade.
 

spice opa cmrr

I'm using T-Spice from Tanner for my simulation. However, T-Spice doesn't have the 'CMRR=VDB(OUT)' syntax, is there any other way to simulate CMRR??

:cry:
 

hpsice cmrr

Hi, Hughes:
Should the DC component of V1 be in the range of common input voltage instead of 0?
 

simulating cmrr

guamak_menanak said:
I'm using T-Spice from Tanner for my simulation. However, T-Spice doesn't have the 'CMRR=VDB(OUT)' syntax, is there any other way to simulate CMRR??

"CMRR=VDB(OUT)" is not needed. You may just use
.PROBE V(OUT)
or the like.

lunren said:
Should the DC component of V1 be in the range of common input voltage instead of 0?
Yes, you are right. The DC component of V1 and V2 should be set to the proper common input voltage.
 

cmr simulation

CMRR only has sense if you make a Monte Carlo analysis. CMRR apperas maily due to mismatch effect that translates the CM varations into an output signal. If all matched transistors were perfect, most of CMRR comes from output conductance of CM current sources (tail current and output branch, for instance).

Just remember that CMRR is an AC manifestation of the DC input offset voltage.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top