Op Amp input offset removing method

[tia_design]

Hi, guys,

How do you guys reduce the input offset for a high DC gain (say 120dB) CMOS Op Amp(VDD=3.3V)? One way is to introduce an auxiliary port parallel to the main port, then the callibration voltage is applied to this auxliiary port. Such method is actually not good for high gain Op Amp.
I found the Texas Instruments TLC4501 CMOS Op Amp (https://focus.ti.com/lit/ds/slos221b/slos221b.pdf) using digital trimming to get as low as 10uV input offset. Does anyone has idea of this scheme? or how can I find related patents or paper?
Thanks very much!

 

[Vamsi Mocherla]

See digital trimming is adjustment of any device parameters after the fabrication. For, example, in the cases of BGRs or some circuits like ADCs or DACs, they will need some adjustements to their resistors, etc for getting an ideal value. Usually, this trimming can be programmed by either link fuse burning or through switches which are controlled by ROMs.

But most importantly your process (fab)should support it. Or else, there is no purpose.

If you want to have a low offset, try and tweak the lengths of the current mirrors or by increasing the areas of the differential pairs.

There is another technique called Chopper stabilization. Here we try to sample the offset in one phase and subtract it at the difference inputs of the amplifier.

I hope that this helps.......