op-amp based bandgap reference problem

• Jun 11, 2014

• #1

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anhnha

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I am designing an op-amp based bandgap reference and getting this problem.

**broken link removed**
**broken link removed**
As Vdd increases, the output of op-amp also increases but at a much higher rate=> Vsg of M11, M12 decrease and the currents flowing through these transistors decrease=> bandgap voltage decreases.

Could anyone tell me how to solve this?

 

• Jun 11, 2014

• #2

Dominik Przyborowski

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Are You sure about proper feedback? Remember that M12 works as another inverting stage. At dc simulation everything works?

 

• Jun 11, 2014

• #3

D.A.(Tony)Stewart

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The design is incomplete without details of characteristics of FETs & R values.

www.circuitsage.com/bandgap/bandgap.pdf

 

• Jun 12, 2014

• #4

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dick_freebird

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Might cut the problem into two pieces by replacing the op amp
with a vcvs of suitable gain; a low quality op amp might just
be showing you the cost of poor PSRR (or, you operating it
at points where its PSRR gets weak).

 

• Jun 12, 2014

• #5

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SIDDHARTHA HAZRA

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anhnha said:

As Vdd increases, the output of op-amp also increases but at a much higher rate=> Vsg of M11, M12 decrease and the currents flowing through these transistors decrease=> bandgap voltage decreases.

Could anyone tell me how to solve this?

Click to expand...

As correctly pointed by Dominik
Is the op-amp connection right? I think you should interchange + and - terminals .... In a band gap the negative feed back loop has to be stronger than the positive feedback loop. The PMOS M11 and 12 provides an additional 180 phase shift. Please check the following docs

https://www.scientificbulletin.upb.ro/rev_docs_arhiva/full7771.pdf
https://web.mit.edu/magic/Public/papers/01692649.pdf

Hope this helps ....

 

• Jun 12, 2014

• #6

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anhnha

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Thank you everyone.

I just check my op-amp connection and it is right. The bandgap is good for input voltage from 2 to 2.9V. However, from 2.9 to 4V, the reference voltage decreases sharply.

- - - Updated - - -

I just tried a vcvs with gain =140000 =103dB that is much higher than my opamp (78dB) but the output voltage curve is still similar to the one above, no improvements.

=> Not opamp problem here.

- - - Updated - - -

Here are the curves of I1, I2, I3 as Vin (supply voltage) increases from 2 to 4V. As you can see I1 and I2 are 100% equal.

 

Attachments

• Bandgap Line regulation test.png

  6 KB · Views: 469
• I1.I2.I3.png

  14.9 KB · Views: 416
• Bandgap_test.JPG

  18.3 KB · Views: 402

Last edited: Jun 12, 2014

• Jun 12, 2014

• #7

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SIDDHARTHA HAZRA

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Hi anhnha,

If you have done the opamp connections correctly .. can you check whether it is a start up issue or not. In a bandgap there are two stable operating points. zero voltage and the other is the required voltage. A band gap starts up by finally falls down because of start up issues. You can check the following paper but you will find a lot of other materials over net you can check them as well.

http://pe.org.pl/articles/2012/4a/67.pdf

Hope this helps ....

 

• Jun 13, 2014

• #8

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anhnha

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Thank you, SIDDHARTHA HAZRA.

I don't think that is startup issue. If there is a startup prolem then the bandgap voltage should be very small (around 0V)? But as in the simulation image, as Vin increases from 2 to 4V, bandgap voltage decreases from 805mV to 799mV. That is not close to zero.

 

• Jun 18, 2014

• #9

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anhnha

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Hi.
Now I need to check the stability of this bandgap using stb analysis in Cadence.
I will insert iprobe in analogLib. However, could you tell me where should I break the loop and insert iprobe?
Also, do I need a startup for this bandgap?


**broken link removed**

 

• Jun 18, 2014

• #10

FvM

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As already mentioned:

The design is incomplete without details of characteristics of FETs & R values.

Click to expand...

We have no chance to check your design. Also BJT areas are important.

 

• Jun 18, 2014

• #11

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anhnha

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Hi,
I used nmos2v and pmos2v in tsmc18rf.
R2 = R3 = 2.03M
R1 = 400K
R4 = 1.75M
Area:
Q1 = 4. 10^(-12) mulitpliter = 1
Q2 = 4. 10^(-12) mulitpliter = 32

 

• Jun 19, 2014

• #12

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anhnha

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Hi.
In some design, I see that there is a capacitor connected between the VDD and the gate of M11. Could you explain about the function of this capacitor?

 

• Jun 19, 2014

• #13

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yuvan

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The capacitor is for high frequency PSRR, when the loop looses its capability to correct for the disturbance and of no help at DC.

But FvM, just curious, why the BJT char is required, it approx always sees close to VBE always so couldn't fully understand why BJT char is required. But I accept we need to know the char of the PMOSes..