[SOLVED] one system,tow different frequency,many process need some help in tinming analysis

hi
i have implement this system contain three part as shown below in vhdl as follow

dcm genertate two freq
synchronizationrocess(CLK3M)
part1rocess(CLK3M,signals)
part2rocess(CLK150MH,signal)
part3rocess(CLK3Mhz,signal)

can anyone give me some time analysis
any warning ,any advice,any suggestion
i am really confuse about this system


the synthisizer report

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 25.668ns (Maximum Frequency: 38.959MHz)
Minimum input arrival time before clock: 4.297ns
Maximum output required time after clock: 4.283ns
Maximum combinational path delay: 3.692ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clks1'
Clock period: 4.937ns (frequency: 202.552MHz)
Total number of paths / destination ports: 1328 / 381
-------------------------------------------------------------------------
Delay: 4.937ns (Levels of Logic = 15)
Source: rfora_-13 (FF)
Destination: lable45/outt3 (FF)
Source Clock: clks1 rising
Destination Clock: clks1 rising

You should just be able to put timing specifications on your clocks, and it should ripple through with most of the timing analysis.

Why do you have other signals in your sensitivity list? do you have a lot of asynchronous sets or resets? or are these signals just synchronous enables or other control logic? if they are synchronous they do not need to be in the sensitivity lists.

if they are synchronous they do not need to be in the sensitivity lists.
all process have the following sentence
if(clk3M; event and clk3M='1') or if(clk15MHZ; event and clk150MHZ='1')
is this mean that the synchronous??

Yes.
You should only have to specify your clock time periods.

Ok .........
:-d