Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

one problem about ModelSim

Status
Not open for further replies.

nineleo

Newbie level 5
Newbie level 5
Joined
Oct 16, 2003
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
54
I wrote a TCL script to compile the verilog file,e.g.

#!/usr/bin/tclsh
exec vlib work
exec vmap work work
exec vlog -fast \
+define+DDR \
# +define+VGA \
top.v \
top_tb.v
there is error in the sixth line(comment line) when run it.
But if change it to c-shell script, there will be ok.
why?
how to correct it?
 

Because TCL shell don't allow a comment inserted between continueing lines. This is consistent with Borne shell and Korne shell. But C shell allow a comment between the continueing lines.

Two possible solutions:
1. Completely delete the line other than commenting-out it, or comment out the line and move it to the end of the command line ( after top_tb.v ).

2. Use cshell.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top