On what frequency the shrinking technology runs ?

Hi,

I always get doubts on "WHAT SHOULD BE THE FREQUENCY...!!!"
My doubt is at what frequency should i synthesize/run/operate
a design if i am working with :
a. 180nm ---> What frequency ?
b. 135nm ---> What frequency ?
c. 90nm ---> What frequency ?
d. 65nm ---> What frequency ?
e. 40nm ---> What frequency ?
f. 32nm ---> What frequency ?
g. 20nm ---> What frequency ?

I know that we cannot run 180nm technology with 1GHz.(Its pessimistic)
Is there any range of frequencies in which each technology lies?
If so kindly list all the ranges of frequencies for the scaled technology
mentioned above ranging from 180nm to 20nm.

Thanks in Advance.
Hoping for Best reply.
Raghava

I only study the IC design for 2 years in school and work for near 1 year. In the other words, I'm not the experienced enough.
However, I can share you with some of my experience until now.

First, the most of all, the fastest operating frequency is based on the complexity of your design.
There are many techniques to enhance the clock frequency such as pipeline, retiming and so on.
But it costs lots of efforts to optimize the design in hierarchy level instead of tool optimization.

For dedicated design, we can push the design operating at 125 MHz for 350 nm process.
( of course, we need to search for the faster hierarchy instead of direct computation )
But for general case , the students ( as TA then ) will design a circuit operated at about 50 MHz.

for general case, the design is targeted at 100 MHz for 180 nm process.
However, 100 MHz is the baseline for 90 nm process. They can be targeted at 160-200 MHz.
for 55nm process, it seems that we can enhanced the design to 300 MHz if there is no memory or macro for tightly timing closure.

The above is all I have experienced. It's not criteria of design guideline.
Currently, I don't the know what is the criteria for a effective design yet.
Hope the one interested in this topic would share your design experience.

Best Regards,
PoLo

YuLongHuang said:

I only study the IC design for 2 years in school and work for near 1 year. In the other words, I'm not the experienced enough.
However, I can share you with some of my experience until now.

First, the most of all, the fastest operating frequency is based on the complexity of your design.
There are many techniques to enhance the clock frequency such as pipeline, retiming and so on.
But it costs lots of efforts to optimize the design in hierarchy level instead of tool optimization.

For dedicated design, we can push the design operating at 125 MHz for 350 nm process.
( of course, we need to search for the faster hierarchy instead of direct computation )
But for general case , the students ( as TA then ) will design a circuit operated at about 50 MHz.

for general case, the design is targeted at 100 MHz for 180 nm process.
However, 100 MHz is the baseline for 90 nm process. They can be targeted at 160-200 MHz.
for 55nm process, it seems that we can enhanced the design to 300 MHz if there is no memory or macro for tightly timing closure.

The above is all I have experienced. It's not criteria of design guideline.
Currently, I don't the know what is the criteria for a effective design yet.
Hope the one interested in this topic would share your design experience.

Best Regards,
PoLo

Click to expand...

Thanks for Sharing your experience.
Hoping for more replies from other ...!

The answer to your questions not very simple or straightforward. It has been partially answered by PoLo and I'll try to complete the rest of it. It depends on the technology node, how efficiently you design or rather type of design. Starting at the basics, the basic gate delay for Fan-out-of-1 gates (FO1) or Fan-out-of-4 (FO4) is determined using Ring-oscillator measurements/simulations. For understanding this, you may use this simple yet effective metric of delay: Td= Ceff*V/Ieff. Where Ceff is the effective gate capacitance (intrinsic+parasitic) and Ieff is mostly less than Idsat (there is a famous IBM paper that discusses the detail of Ieff).

Now lets assume you start at 180nm technology node. The gate capacitance per micron of transistor width and the current it can drive (Ceff and Ieff) and the nominal voltage (V) will determine the delay of a single FO1 or FO4 gate. This is inverter delay, so basically the best delay you can get for that technology. If you had your design comprising of only inverters (unrealistic), this is the max frequency you'd hit in that technology. However, you'd have to use NAND/NOR/XOR/MUX etc. to get something useful. So, assuming you plan to do a synchronous design the amount of logic you decide to put between to FLOPS will determine the clock frequency. The delay of logic + Setup/Hold time constraints of the FLOPs will determine what clock frequency you should set.

However, that is not the end of the story. You can go for architectural enhancements such has Pipelining to increase your efficiency and get better computation per clock. Additionally, I am assuming that you use basic combinatorial logic between flops. If you decide to use Dynamic Logic gates (Domino logic, for example), you can definitely hit higher frequencies to implement the same logic. As you can clearly see, for a given technology, there are numerous factors that'll determine the clock frequency you can hit with the design. If I remember correctly, Intel hit frequencies in the range of 1.4GHz with a Pentium 3 using 130nm technology. But they had variants at 400 MHz as well. So how do you determine what frequency corresponds to what technology node?

So once you start shrinking your node, from 130nm to 90nm, the main advantage used to be that you could get 50% lower area, about 2X performance at the same power, or 50% lower power at same performance. Not anymore...first of all due to power constraints, designers started migrating towards multi-core implementations where the performance of each core is limited to about 1.5~2GHz. The new generation of processors, mainly the ones used in mobile phone/tablet space, the idea is to hit max frequencies in a very low power budget so that battery life can be extended. You'll see most designs implemented in the 32/28nm node (the most recent one) operating in the range of 1 - 1.6GHz to keep power within limits. However, these designs can be pushed up to 2GHz at higher power dissipation.

Another issue coming up at shrinked nodes (28nm and lower) is the issue to actually manufacturing or lithography limitations. Scaling transistors is not what it used to be 5-7 years ago. In the last few nodes, gate length scaling has stopped, the metal pitch and poly pitch are the two main parameters being scaled. Lithography limitations require designers to use regular layouts and lots of restrictions in design to successfully fabricate chips. All these issues result in some loss in performance compared to the fully custom, less restrictive designs up to 40nm node.

Summarizing, the answer to your question is that there is definitely a max frequency you can hit in a technology node, however there isn't one clear answer. I can quote the max ring-oscillator frequency you might get at each node, but that does not represent what you'd get in a design. However, the max ring oscillator frequency at a given technology node represents the speeds the technology node is capable of going up to, and that increases with shrinking. For more information, some numbers are provided in the Digital CMOS Design textbook by Weste Harris. Actual designed frequency depends on a lot of factors, as I tried highlighting in my answer.

Hope this helps, please let me know if you have any follow up questions.

Usually, what happens is, as the length is shrunk , the FET starts behaving more like a resistor than a transconductor. Because of this, the gate oxide in smaller length FETs is made thinner to increase Cox (gm increases with Cox). So, for the same area, the reduction in capacitance is actually not as high as you expect.

For a given transistor, there's a frequency called "ft",where the current gain is 1. i.e, you give a sine wave at the gate of the mosfet and measure the current through the gate and the current through the drain. At DC, the FET has an infinite input impedance (the current through the gate is 0). At high frequencies, the impedance due to Cgs starts decreasing and gate current can be seen.

The formula for ft is ft= gm/(2*pi*Cgs) . gm is the transconductance. As it can be seen, even with a 600nm tech node, you can still support 1GHz, provided you burn enough current (theoretically).

When the length is decreased, the capacitance is marginally lowered. Because of this, the mos can support a higher frequency of operation without as much trouble.

saurabhr8here said:

If I remember correctly, Intel hit frequencies in the range of 1.4GHz with a Pentium 3 using 130nm technology. But they had variants at 400 MHz as well.

Click to expand...

First thanks for your kindly replay.

If it's right, the operating frequency for 1.4GHz using 130nm technology is really amazing.
It sounds that it's much like analog design instead of digital design.
It means that the designer will elaborate the every combinational logic to reach this clock rate.
This is not only the architectural level ( or algorithm ) optimization but also gate level optimization.
The operating rate for a 32-bits adder may even challenge this goal.
I realize that why there are more and more stage such as 14-stages for in CPU design.

Yes, YuLongHuang: there was extensive gate level optimization. Additionally at 90nm, Pentium 4 was probably the fastest designed general purpose microprocessor ever created by Intel. It used low voltage swing logic (similar to domino) and some of the circuit techniques have never been used since, mainly because it burned a lot of power and getting to sign off on the design was a tough job. The processors were clocked at 3.8 GHz using a conventional fan and probably overclocked up to 4GHz with liquid cooling. Intel and AMD have since then shown higher clock speeds, but the circuit techniques used in the P4 design and their contemporaries in AMD are unparalleled.