On what basis is the cell row height fixed in the semi custom physical design

[jagz]

Hi,
On what basis is the cell row height fixed in the semi custom physical design. Since the length of the transistor is based on the technology, and the width could vary if the nmos or pmos is fingered, the cell row height cannot be completely based on these. So which factor of the standard cell or the transistor determines the cell row height.

Thanks

 

[erikl]

The height of the standard cell library + some additional space for inter-cell routing.

 

[yadavvlsi]

Most place-and-route tools require that the height and width of a standard cell be an integer multiple of the vertical and horizontal wire track. The height of the standard cell is the same throughout the library, but their widths vary according to their logical functions and drive strengths. A typical standard cell for the Complementary Metal Oxide Semiconductor (CMOS) process is composed of a row of NMOS (N-type transistors) with channel width n W , and a row of PMOS (P-type transistors) with channel width p separated by the distance of the P and N diffusion (or active) area. W The P and N diffusion area spacing, the channel width of PMOS and NMOS transistors, and the width of power (VDD) and ground (VSS) buses are the key parameters in determining the height of standard cells. Figure below shows a generalized standard cell height concept. Height of a stranded cell is the height of row..