erik_xfan
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set clock latency in DC
Assume that we have a top-level design TOP, which consists of two subdesigns A and B. A clock signal CLK is defined in TOP. Can we specify the clock propagation delays, from CLK to the flipflops in A and B, respectively, which are different from each other?
Solutions on RTL or netlist are both OK!
Thanks a lot!
Assume that we have a top-level design TOP, which consists of two subdesigns A and B. A clock signal CLK is defined in TOP. Can we specify the clock propagation delays, from CLK to the flipflops in A and B, respectively, which are different from each other?
Solutions on RTL or netlist are both OK!
Thanks a lot!
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