On chip variation when applying voltage scaling in timing closure

[Rafq]

Hi all, is there any way to handle on chip variation for a design which voltage scaling is applied?

Lets assume AOCV model is used that provided by the foundry for a very specific operating voltage and temperature, then of course we do voltage scaling for unavailable library.

Therefore, any recommendation to handle this kind of intra-die variation?

 

[dick_freebird]

There's variation and there's variation, multiple dimensions for
you to decide which (or how many) matter and how much.

You have "make" (VT, delta-L, etc.) cross-die gradients and
random and proximity effects.

You have I*R drops which can alter span or offset of logic
thresholds and drive strength

You have thermal gradients between high power density and
low poweed density blocks.

The foundry can tell you about #1 (if motivated). The rest
need you to estimate actual, or set boundaries to meet that
say "no prob".

How that all gets implemented in a Big Digital Design Flow,
that's for somebody else.

 

[ThisIsNotSam]

Hi all, is there any way to handle on chip variation for a design which voltage scaling is applied?

Lets assume AOCV model is used that provided by the foundry for a very specific operating voltage and temperature, then of course we do voltage scaling for unavailable library.

Therefore, any recommendation to handle this kind of intra-die variation?

You can always do the old flow, without AOCV margins, which will be very pessimistic.