flote21
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Programable Termination resistance Cyclone IV FPGA
Hello people!
I am generating a 150 MHz clock with a 3.3V-LVTTL I/O FPGA pin and I want to know if it is possible to programm a internal source resistance of 50 Ohm to avoid reflections and other issues. If this is not possible then, I would like to know which the default Zo of the I/O pins.
Thanks!
Hello people!
I am generating a 150 MHz clock with a 3.3V-LVTTL I/O FPGA pin and I want to know if it is possible to programm a internal source resistance of 50 Ohm to avoid reflections and other issues. If this is not possible then, I would like to know which the default Zo of the I/O pins.
Thanks!
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