Omitting SRAM control signals

[whack]

Got a minimalization/reduction question here.

I'm trying to reduce the number of control pins necessary to control an SRAM with an FPGA.

I've got three SRAM parts here that should theoretically be interchangeable. All three are 10ns 512Kx16 3.3v SRAMs in TSOP44 package.
ISSI IS61WV51216EDBLL-10TLI
https://www.issi.com/WW/pdf/61-64WV51216EDBLL.pdf
Cypress CY7C1051DV33-10ZSXI
https://www.cypress.com/?docID=31427
Alliance AS7C38098A-10TIN
**broken link removed**

They have the following control signals:
/CS - chip select, active low
/OE - output enable, active low
/WR - write enable, active low
/LB - lower byte enable, active low
/UB - upper byte enable, active low

I am trying to reduce the number of signals and pins I use. I believe since I will always use 16-bit wide input/output I should be able to connect the /LB and /UB pins to ground permanently.
However, I was looking at timing diagrams and I'm not 100% certain if I can permanently connect /CS to ground.

Basically my question is, can I control an SRAM like this one with just /OE and /WR for reading and writing and have the other three control pins wired to ground? Or would I have to change the state of the /CS pin?

I'd like to be pretty certain about this because if I can get away with doing it this way I won't route those to FPGA on PCB. Mistake would be a difficult fix there.

Insight is appreciated.

 

[FvM]

Yes, you can pull /UB, LB and /CS permanently low and use only /OE and /WR signals. Static power consumption might slightly increase, review the datasheet.

 

[KlausST]

Hi,

If you want to reduce signals, why don' you use 8 bit data?...this saves 6 lines..

Klaus

 

[whack]

Yes, you can pull /UB, LB and /CS permanently low and use only /OE and /WR signals. Static power consumption might slightly increase, review the datasheet.

Thanks.

Static as in idle? Fortunately this circuit will never idle, it's constantly reading and writing, other times the system is powered off completely.

EDIT:
Just read up on static vs. dynamic power dissipation. So you're saying power consumption goes up because there would be no AC activity on those pins? Even if they would end up being active on every cycle?

Hi,

If you want to reduce signals, why don' you use 8 bit data?...this saves 6 lines..

Klaus

You meant to say "save 8 lines"? These chips have 16-bit data bus. 16-8=8

If I wanted to work with 8-bit data I would get a chip with 8-bit word, those are available. My input data is 12 bits, and I need to read or write that much on each access.

Depending on which design philosophy I end up employing, I may not route data through FPGA at all, so how many data lines my design has won't affect I/O pin count on the FPGA in that scenario.

 

[KlausST]

Hi,

16 - 8 = 8, true.

But then you need 2 additional control lines.
8 + /LB + /UB = 10

-> you save 6 lines.

Klaus

 

[whack]

Hi,

16 - 8 = 8, true.

But then you need 2 additional control lines.
8 + /LB + /UB = 10

-> you save 6 lines.

Klaus

I'm looking at the block diagram for those chips and what you describe will not allow working with 16-bit word using 8 data lines. The block diagram does not show upper and lower byte muxed or demuxed.

I'm pretty sure I want my 12 bits of data in parallel, but for the sake of discussion please elaborate.

- - - Updated - - -

I guess they are muxed/demuxed internally but that's not indicated on the block diagram. The Cypress datasheet describes the behavior in written description however.

 

[FvM]

I guess they are muxed/demuxed internally but that's not indicated on the block diagram.

Are you talking about the x16 SRAM? There's nothing multiplexed, it has full 16 bit data bus inside.

I must confess, I don't actually understand what's unclear with x8 versus x16 bit SRAM access. The obvious difference is data throughput. If you have 12 or 16 bit data but write it using 8 bit accesses, you need double time.

 

[whack]

Are you talking about the x16 SRAM? There's nothing multiplexed, it has full 16 bit data bus inside.

The way datasheet describes it you could write the upper byte into lower byte's position using the byte controls. I have no use for it either way but KlausST finds that functionality valuable for some reason.

I must confess, I don't actually understand what's unclear with x8 versus x16 bit SRAM access. The obvious difference is data throughput. If you have 12 or 16 bit data but write it using 8 bit accesses, you need double time.

Oh yeah, that's crystal clear. I don't want multi-cycle access for sure.

 

[FvM]

The way datasheet describes it you could write the upper byte into lower byte's position using the byte controls. I have no use for it either way but KlausST finds that functionality valuable for some reason.

Flipping the byte positions would in fact require a multiplexer, but that's not the usual purpose of /UB and /LB control signals, and as far as I see not said in the ISSI datasheet.

/UB and /LB are used if a processor with 16 bit data bus want's to write single 8 bit data entities, e.g. char variables. The address lines are selecting both high and low byte, you need an additional qualifier along with /WE to tell if lower, upper, or both bytes should be written.

 

[KlausST]

Hi,

with /UB and /LB control you externally connect:
IO0 with IO8
IO1 with IO9
IO2 with IO10
IO3 with IO11
IO4 with IO12
IO5 with IO13
IO6 with IO14
IO7 with IO15
of the SRAM.

now you have an 8 bit wide external data bus.

You need two write cycles, one for lower byte, one for upper byte.

Klaus

 

[FvM]

now you have an 8 bit wide external data bus.

You need two write cycles, one for lower byte, one for upper byte.

Or preferably buy a cheaper 8-bit wide RAM.

 

[whack]

Or preferably buy a cheaper 8-bit wide RAM.

I wonder why nobody thought of that before.

 

[ads-ee]

EDIT:
Just read up on static vs. dynamic power dissipation. So you're saying power consumption goes up because there would be no AC activity on those pins? Even if they would end up being active on every cycle?

No the static power is the power increase due to the /CS being constantly enabled is due to the I/O buffer being always enabled. The /CS pin either connects the core of the SRAM IC to the pins or disables them. This is different than the /OE (tri-state). I'm pretty sure the difference is probably negligible.

You'll see more static power improvement by switching from a 16-bit part to an 8-bit part, but that will be offset by much larger dynamic currents (2x switching speeds to match the 16-bit device).