tibs
Junior Member level 2
Hi all,
I want to design a analog variable gain amplifier. So I use a JFET (n channel) used in a variable resistor. (cf SCH.ZIP).
Into the sch.zip, you can find the result from the simulation (wave.jpg). The gate voltage is polarized @4Vdc. The V1 source is a square 100Hz, 100mV PP with no offset (eg +50mV, -50mv).
As you can see, there is an offset on Vout (100Hz, 960mmV PP with 25mV offset (eg +468mV, -493mv).
Does anyone know why there is an offset? I don't understand.
Best regards,
Christophe.[/img]
I want to design a analog variable gain amplifier. So I use a JFET (n channel) used in a variable resistor. (cf SCH.ZIP).
Into the sch.zip, you can find the result from the simulation (wave.jpg). The gate voltage is polarized @4Vdc. The V1 source is a square 100Hz, 100mV PP with no offset (eg +50mV, -50mv).
As you can see, there is an offset on Vout (100Hz, 960mmV PP with 25mV offset (eg +468mV, -493mv).
Does anyone know why there is an offset? I don't understand.
Best regards,
Christophe.[/img]