Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

offset voltage in dynamic comparators

Status
Not open for further replies.

Eng.takwa

Newbie
Newbie level 1
Joined
Apr 18, 2023
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
15
Hi every one ,
Can somebody explain how to use the Monte Carlo approach in the LTSPICE simulator to get the offset voltage for clocked comparators?
 

First you need a testbench which will give you a proper
Vio measurement for one single run. Then MC analysis
is just setting up loops and storing T*V*P datapoints for
statistical treatment.

I expect this will have to be a transient analysis as you
can't do clocks in any other, the kickback noise can be a
real significant element (high Z sources bad, low Z sources
good, but what is real application?).

A classical op amp test loop can turn comparator chop
into a proxy (up-scaled for measurement, then attenuated
back down) feedback voltage. This runs slow. A filter, maybe
behavioral, and a vcvs might work out for you - what you
need is a converging series of feedback events closing the
loop, not necessarily full precision op amp detail including
its slowness.

If your need for accuracy is modest then a ramp from Vid(min)
to Vid(max) @ Vcm (cases) might be more time efficient. Need
ramp to be well slower than prop delay. But you don't need to
out-wait a DC precision op amp's compensation-as-delay at
least.

Now what LTSpice has for MC support, I have zero idea.
I'd bet that there's plenty about it on the LTSpice 'boards.
I've been using ngspice.
 




 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top