Offset in Post-layout simulations

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moisiad

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Hi all

After transient post layout simulations on a comparator i have noticed that an offset voltage of 50mv exists, which is not visible in schematic level.

It is strange since the layout is symmetrical, and any offset should arrise from mismatches between the transistors. However during any transient post layout simulation noo mismatches are included (only in Monte Carlo analysis).

Have any of you noticed such an effect?

Thanks in advanced
 

Did your layout pass LVS? Did you run extraction with parasitics or without?
 

it seems that there are some error in your layout.
check your lvs result first.
 

The layout has pass LVS. The post simulations include RC parasitics
 

maybe the parasitic capacitors don't match
 

Just for your info

The offset was due to parasitic capacitance of two internal nodes of the comparator with the VDD and GND lines which was 0.5um left and rigth of the circuit. The parasitic capacitances was almost 1fF !!!
It seems that analog design becomes realy hard in submicron technologies (90nm)
 

the layout is very important to drcease the offset
 


transient post simulation?
Maybe it is a measurement error because of the delay time.
 

Generally the problem is due to the drop on the critical nets.So if u increase the routing widths of the critical nets like the connections to the current mirrors, diff pairs,VDD lines and the output nets.Also the placement of the pins matters.If u make this changes to ur layout i think u can come out of the problem.

regards,
vijay
 

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