moisiad
Member level 4
Hi all
After transient post layout simulations on a comparator i have noticed that an offset voltage of 50mv exists, which is not visible in schematic level.
It is strange since the layout is symmetrical, and any offset should arrise from mismatches between the transistors. However during any transient post layout simulation noo mismatches are included (only in Monte Carlo analysis).
Have any of you noticed such an effect?
Thanks in advanced
After transient post layout simulations on a comparator i have noticed that an offset voltage of 50mv exists, which is not visible in schematic level.
It is strange since the layout is symmetrical, and any offset should arrise from mismatches between the transistors. However during any transient post layout simulation noo mismatches are included (only in Monte Carlo analysis).
Have any of you noticed such an effect?
Thanks in advanced