Offline Flyback: Isolation Creepage and clearance on inner layers?

[cupoftea]

Hi,
We are doing a 24Vout offline flyback 1A.
We wish to use Inno3-CE controller. (link below)
We have a 4 layer PCB.
So on page 15 of this...

https://www.power.com/sites/default/files/documents/innoswitch3-ce_family_datasheet.pdf

...should we have our internal copper layers running under the transformer, so as to shield
the Innoswitch from the transformer?
As you know, clearance/creepage distances for internal copper layers are much shorter, so I believe we can
have internal layer 2 primary copper as near as 3mm away from internal layer 2 secondary copper pour?
What about going even further, and completely shielding the innoswitch from the transformer by having layer 2 copper
pour coming right from primary to secondary side, and layer 3 copper pour coming from secondary
to primary side?

Also, does the spark gap prevent damage to the innoswitch due to hipot tester voltage going
well over 4kv due to the reaction with the y capacitor across the transformer?

Would it be Ok for us to put the spark gap on an inner layer? If so then how far apart should be the primary and secondary side pointed copper bits?

Also, in a no-fan , small , totally enclosed (no vents) plastic enclosure, with the size of source copper pour
shown in page 15 (above), what temperature would you say the Innoswitch would rise to? (40 degC ambient)

 

[FvM]

Also, does the spark gap prevent damage to the innoswitch

No, but it would thwart safety qualification.

Would it be Ok for us to put the spark gap on an inner layer?

Never.

 

[cupoftea]

Thanks, as you know, the relative permittivity of solder resist and pre-preg etc, is less than that of air, so you would think that an inner layer spark gap would arc over more readily then a top layer spark gap? (considering they both had the same coper to copper distance).

..or is that the wrong way of looking at it?...and the capacitance (air capacitor) is actually less with a top layer spark gap, so it more readily flash's over than an inner layer spark gap?

Also, would, if possible, much appreciate any possible google search terms for finding out what is the minimum distance allowed between inner copper layers on primary and secondary of an offline SMPS? Have searched far and wide but do not find as yet.
Outer copper is pretty well 6mm of clearance required across the isolation barrier. But for inner layers its much more difficult to find the minimum allowable distance.

 

[FvM]

Any spark gap involving PCB material along the discharge path causes tracking and is unsafe by design. If useful at all, a PCB spark gap must be designed with an air gap over a milled slot. I have seen such spark gaps on old 10BASE2 (coax "thin wire") ethernet interface boards.

--- Updated Aug 27, 2024 ---

Safety standards, e.g. IEC 61010, have requirements for internal PCB isolation clearance and minimal substrate thickness. There also IPC standards and manufacturer suggestions regarding HV PCB design.

 

[KlausST]

Hi,

and still then it depends on the energy that has to be "disspated".
The higher the energy, the higher the mass of the vaporized metal

To decrease the spark voltage you use geometry with sharp edges pointing to each other (to increase local electric field strength).
But at every spark a bit of the sharp edge will be vapurized --> resulting in spark voltage to get higher and higher each time.

Other parameters have influence: altitude, dirt, air flow, humidity, PCB production ....

All in all: it´s so unreliable, thus for me no option.

Klaus

 

[FvM]

I completely agree about unreliable operation of spark gap overvoltage protection (that's the meaning of "if useful at all" above). Furthermore, safety standards have no room for overvoltage protection elements like TVS diodes, varistors or spark gaps across safety isolation barriers.

 

[cupoftea]

Thanks, that sounds good. As you know, the actual PCB copper on either side of the isolation barrier will, at some voltage, become a "spark gap" anyway.
What you kindly said about tracking across PCB material was interesting. We have a customer-sent-in PCB which is flashing over on hipot test. I just wonder if one applies 4kv rms from a hipot tester to a PCB with 6mm of clearance between primary and secondary...then if you keep applying it, then eventually it will just flash over anyway (at some point). And then, if the 4kv rms is kept being applied, then eventually a conductive trace will "burn" into the PCB, and it will then flash over at much lower voltage than 4kv rms?

 

[marce]

IPC-2221 Table 6-1, for basic clearances... Creepage is usually covered by an ISO/EN spec and is larger than basic clearance. Crepage only applies to outer layers though. Done high voltage supplies on FR4, 35kV+, but special requirements required, such as special potting.
Spark gaps, there are design guides, have to be on outer layers, no solder mask, triangular pads, with points facing each other... Last put them on a design years ago, for wide area network protection board for CCTV cameras on metal poles in urban situations etc. Not much use, think they were in the design spec, so had to be added, protection against lightening (LOL), in tests a lightening strike pretty much destroyed the protection board and a few other bits, basically the metal pole survived...
Even though inner layer clearances are less than external layers, it is always bets to have a visible, well defined isolation barrier on a board. It should be instantly obvious as a clear path through all layers.
Safety FIRST...

 

[cupoftea]

Thanks, supposing a gap on the top copper flashed over on a PCB with 4kv hipot test. What distance do you think would flash over on the inner layers on the same PCB.....?....about 150% of that distance before inner layer gap would flash over?
I know its greater distance for the flashover on inner layers, but do you know roughly as to what proportion?

 

[KlausST]

Hi,

I know its greater distance for the flashover on inner layers,

You know?
It´s greater?

From an internet source:

As a general rule-of-thumb, the dielectric strength of an epoxy is roughly 500 volts/ mil at 23°C for an insulating product. As a practical example, if an electronic circuit needs to resist 1000 volts, a minimum of 2 mil of dielectric epoxy is required.

The dielectric stregth of glass and epoxy (inner layer) is way higher than of air (outer layer) . Thus the gap becomes smaller according my (and internet) understanding.

The problem is: It depends on purity of matrieals and the quality of lamination of the PCB. Bad lamination may introduce humidity or air bulbs, which will make an spark to flashover earlier (lower voltage) than with perfect lamination.

Klaus

 

[FvM]

Dielectric strength is relevant as absolute limit value for tests, clearance will be designed for working voltage + transients in the first place. Internal PCB clearance requirements in standards are quite different, e.g. for 800V working voltage 200V/mil in IEC61010 and 20 V/mil in IPC. Latter value is obviously reflecting problem of non-homogenous substrates. Manufacturer suggestions for horizontal inner clearance are as low as 8V/mil. Consider that internal "flash over" of solid insulation means PCA non-repairable damage.

 

[KlausST]

Hi,

OP says "creepage and clearance on inner layers".
In my eyes this does not exist.

Creepage is the shortest distance on the surface (with one side "air"). So dirt from air (in worst case metallic = conductive) will continously lay down on the surface and will make the surface slightly conductive. So over the years the surface can widthstand less and less voltage. And some day the dirt on the surface is conductive enough for a spark to jump over.

Clearance is the sortest air gap between two conductive parts. With no need of a surface. (mind: solder stop layer is NOT considered as valid insulation. It is treated as air)

I don´t think that "creepage" is valid terminology for inner layers. It needs a surface (to get dirty with time) and air on the opposite.
I also don´t think "clearance" is valid terminology for inner layers, because it also needs "air".

There is no destiction between creepage and clearance at all.
But - as FvM already mentioned - there is
* horizontal distance = between layers
* vertical distance = at the same layer

Klaus

 

[cupoftea]

Thanks, Pg 138 of EN61010 as below states that for CAT IV (overvoltage), the creepage and clearance values are exactly the same
for inner PCB layers as outer PCB layers, regarding Basic, Reinforced or supplementary insulation across eg
a SMPS transformer isolation barrier. (it refers one back to table K.4 on page 134.)

This is quite interesting....so...when you involve a mains isolation barrier...the fact of being on an inner layer
affords one no reduction at all, in isolation distance needed. For CAT IV, it is 5.5mm, be it inner layer, or outer layer.

EN61010

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwjq4N6orpqIAxXKZkEAHQipATs4ChAWegQIEhAB&url=http%3A%2F%2Fdfv-technologie.com%2Fdoc_technique_dfv%2Fnormes_afnor%2FCEM%2FEN%252061010-1%25202010%2520Electrical%2520safety%2520for%2520laboratory%2520equipment%2520-%2520General.pdf&usg=AOvVaw0xt5knc9St64GARNeuPWV4&opi=89978449

 

[cupoftea]

All in all: it´s so unreliable, thus for me no option.

Thanks, in that sense concerning spark gaps, i tend to agree with yourself.
The thing is, its nice to do a 4kV hipot test on every product so that you can boast to your customers that you do so.
The 4kV will actually do some damage to the product, even if only applies for one second.
-But with a spark_gap_with_Slot, the damage will be less. And that sounds like worth having , i dont know if you would agree?

This is want Power Integrations say about it on their forum... (concerning their innoswitch offline flyback SMPS controller which is mounted straddling the pri-sec isolation barrier...

Introducing a spark gap on your board prevents damage to the InnoSwitch device during Hipot testing, as the energy that would normally pass through the device will instead pass through the spark gap. However, this does not guarantee that your entire system will pass the Hipot test. Our InnoSwitch3-CE is tested to withstand Hipot testing up to 4 kV.

..So Power Integrations do appear to believe that the hipot test does less damage to the componentry when you have a spark gap on the PCB.

 

[FvM]

Pg 138 of EN61010 as below states that for CAT IV (overvoltage), the creepage and clearance values are exactly the same
for inner PCB layers as outer PCB layers

Not at all. Pg 138 isn't talking about conductor spacing, only voltage rating (test voltages).

I don´t think that "creepage" is valid terminology for inner layers. It needs a surface (to get dirty with time) and air on the opposite.
I also don´t think "clearance" is valid terminology for inner layers, because it also needs "air".

Creepage doesn't exist on inner layers, the term clearance is however used for internal conductor distance in some standards, e.g. IPC 2221A. IEC 61010 avoids it for inner layers.

 

[cupoftea]

Hi, the following thread appears to confirm that the hipot test voltage is higher due to the ringing between the common mode choke and the y cap. Please can you confirm this?

https://www.power.com/community/for...-gaps-across-innoswitch-and-common-mode-choke

So for example a 4kVrms hipott test woudl normally peak at 5.6kV, but due to the Ycap/common mode choke interaction it will be significantly higher?

 

[FvM]

If at all, LC ringing is relevant for surge test, not for AC or DC Hipot test. If your test spec involves surge test, check in simulation if your circuit has a high Q ringing problem.

 

[D.A.(Tony)Stewart]

There is no ringing problem when you test with DC 41% higher using a slow ramp
The surge test is analyzed from a measure of amount of voltage amplification from resonance but the real criteria is insulation breakdown which may have Partial Discharge as a precursor.

The link suggests that the spark gap in CM chokes can only handle low energy surges of ESD.

Some people prefer the medical grade CM filters without Y caps

Perhaps the spark gaps are to bypass overvoltage which could damage the insulation of the magnet wire and then be protected by a blowing fuse from follow-on grid current or just dissipated if low energy ESD. A TVS would seem safer with inductive high impedance to a narrow pulse than an unfused arcing gapped core. A 1us pulse might not ionize a 4kV air gap until 20kV.

I would worry if gap arc self dissipates or triggers an SCR latching effect on the grid from the short.