Although I don't have hands-on experience in this area...
I've experimented with simulations to explore what happens in regard to power factor.
(1) The first schematic has a resistive load, 3kW.
Waveforms of supply V and A are in sync (optimal condition).
(2) Load is resistor and inductor in series. Values adjusted to receive same Ampere level.
Supply V waveform is out of sync with supply A waveform. Notice the load calls for high Amperes at a time when supply V is low. This is not optimal. Performance may suffer.
(3) PFC capacitor added. It performs 'give and take' action in the power loop.
This restores synchronization of the supply V waveform to supply A waveform.
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There may be a glitch in the simulation, in the sense that supply C only produces 9A, yet the load receives 18A. I'm not sure I can make sense of this. Although it may throw off the numerical figures, nevertheless the concept itself should still be valid.