DDR3 has programmable ODT resistors, they'll be selected according to bus topology and placement of the respective RAM chip, e.g. enabled at end position. The setup in simulation should reflect the ODT settings in real circuit. If you haven't yet chosen it, review DDR3 design guide. I'm presuming that Zync DDR IP has no restrictions in controlling ODT settings, but I'm not familiar with it. In case of doubt Xilinx reference designs have suggestions for ODT settings respectively default settings that can be reproduced in simulation setup.