ODT setting in SI simulation

[aminpix]

I am using hyperlynx to simulate my DDR3 layout. I have two DDR3 connecting to a Zynq FPGA.

When I want to simulate my design, I have to set my data pins at DDR3 side and choose one of these models:
DQ34_ODT0
DQ34_ODT20
DQ34_ODT30
DQ34_ODT40
DQ34_ODT60
DQ34_ODT120
DQ40_ODT0
DQ40_ODT20
DQ40_ODT30
DQ40_ODT40
DQ40_ODT60
DQ40_ODT120

How can I figure out which model I should select for my DDR_DQx pin?

I will appreciate if you refer me any useful resource online.

 

[FvM]

DDR3 has programmable ODT resistors, they'll be selected according to bus topology and placement of the respective RAM chip, e.g. enabled at end position. The setup in simulation should reflect the ODT settings in real circuit. If you haven't yet chosen it, review DDR3 design guide. I'm presuming that Zync DDR IP has no restrictions in controlling ODT settings, but I'm not familiar with it. In case of doubt Xilinx reference designs have suggestions for ODT settings respectively default settings that can be reproduced in simulation setup.