beeflobill
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While working on a project I found an odd Verilog simulation behavior that I wasn't expecting. I thought it was interesting because it was so unexpected to me, and I thought that others might appreciate a ( at least a useful ) reminder of what seems to be subtle Verilog behavior. I do have a couple of questions, what is the technical name for this behavior (if there is one), and is this sort of thing simulator specific or firmly set?
I ran the code below and obtained the output:
I was really expecting to see something like:
because I was I thought 'a' would immediately update from the assign statement, but I see that the assign statement isn't updating until the end of the timestep.
Thanks
I ran the code below and obtained the output:
a=x b=0
a=1 b=0
a=1 b=1
a=1 b=1
a=1 b=0
a=1 b=1
a=1 b=1
I was really expecting to see something like:
a=1 b=0
a=1 b=0
a=0 b=1
a=1 b=0
a=1 b=0
a=0 b=1
a=1 b=0
because I was I thought 'a' would immediately update from the assign statement, but I see that the assign statement isn't updating until the end of the timestep.
Code:
module bench();
reg b;
assign a = ~b;
initial begin
b = 0;
$display("a=%b b=%b", a, b);
#10;
$display("a=%b b=%b", a, b);
b = a;
$display("a=%b b=%b", a, b);
b = a;
$display("a=%b b=%b", a, b);
end
endmoduleThanks