nxm SHIFT REGISTER IMPLEMANTATION BY VHDL

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity nxmBitShiftReg is
generic (n : integer:=4;
         m : integer:=8
);
    Port ( CLK : in STD_LOGIC;
           CE : in  STD_LOGIC;
           SR : in  STD_LOGIC;
              OPMODE : in STD_LOGIC_VECTOR (1 downto 0);
              SRINIT : out STD_LOGIC_VECTOR ( m*n-1 downto 0);
           DIN : in  STD_LOGIC_VECTOR (m-1 downto 0);
           DOUT_mreg : out  STD_LOGIC_VECTOR (m-1 downto 0); -- output of multiplied registers
              DOUT_f : out STD_LOGIC_VECTOR (m*n-1 downto 0)
              );
end nxmBitShiftReg;
 
architecture Behavioral of nxmBitShiftReg is
type DIN_in_unit is array  ( n-1 downto 0 ) of STD_LOGIC_VECTOR ( m-1 downto 0 )  ;
type DOUT_out_unit is array  ( n-1 downto 0 ) of STD_LOGIC_VECTOR ( m-1 downto 0 )  ;
signal i : integer;
 
component m_bit_register
Port (     CLK : in STD_LOGIC;
           SR : in  STD_LOGIC; 
           DIN_reg : in  STD_LOGIC_VECTOR (m-1 downto 0);
           DOUT_reg : out  STD_LOGIC_VECTOR (m-1 downto 0)            
              );
end component;
begin
multiple_registers : for i in 0 to n-1   generate   --register instantiation n times
    begin  --"begin" statement for "generate"
     Registr : m_bit_register
     PORT MAP ( CLK => CLK ,SR=>SR , DIN_reg=>DIN_in_unit(i), DOUT_reg =>DOUT_out_unit(i) );            
end generate multiple_registers;
end Behavioral;