[SOLVED] NWELL_STampErrorMult, ErrorConnect, HNWELL_StampErrorMult, ErrorConnect

Hi guys,

I am designing a rough bandgap layout (to try some stuffs) and when I run the DRC a get those erros that I posted in the thread title.

The layout is in here:



The thing is that when I simulate in a new layout each of the highlight parts there is no DRC error. Well, the orange one, without those M1_PACTIVE contacts doesn't give any error.

What might be happening? Thanks in advance.

(H)NWELL_StampErrorMult, ErrorConnect usually means you have several (more than one) (H)NWELLs on same voltage level, but (each or any one!) not connected by an n+ bulk contact via metal to the same voltage (e.g. VDD).

Separate (H)NWELLs with PMOS transistor source not at VDD level also must have an n+ bulk contact connected via metal to the source.

I am so sorry erikl, but I didn't understood anything what you said. I am really sorry.

Can you explain by other means?

For example, one of the things that is blinking (error) is the NWELL it self. Here you can see with more detail some of errors:



Another example: It is supposed to put the BJT transistors inside the NWELL. When I ask cadence to present only the NWELL's it seems that the BJT has an NWELL. Or my eyes are fooling me or I don't know.

Regards.

EDIT: erikl, I have tried to pull the NWELL from th BJTs transistors and the error has disappeared. Can you explain why? I thought that the BJT had a well and that this well should be place in the same well as the MOST. Please, can you explain both?

You know what bulk means? Bulk is the "substrate" where the transistors are in: it's the p-substrate for NMOS, resp. the n-well for PMOS. Any (or each) "substrate" must have one or more highly doped (i.e. p+ for the p-substrate, and n+ for the n-well) contacts adjacent to or near the source of the transistors in their bulk, and these contacts must be connected by metal to the appropriate voltage level, which is (usually) GND for the p+ p-substrate contacts resp. VDD for the n+ n-well contacts.

If this isn't done correctly, you get such StampErrorMult & ErrorConnect errors.

Yes I know what bulk is. I just didn't understood well what you wrote (maybe my english). But I solved that. Thanks!

I am sorry, but I never worked with BJT, that's why I am asking this because is kind confusing.

Now I have another problem. This might be because of the BJTs.

Device dion_l130e(DIO) on layout is unbound to any schematic device.

UnBound devices found.

I found the problem. This is the result of working at very late hours.

The problem is that I was inserting the BJT inside the NWELL. Because the colletor of the BJT is the outer most layer, he was forming a diode.