nwell resistor terminal discrepancy. (IBM process). LVS error.

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EsperanzaL

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Hello,

I am quite new to layout and I am using IBM technologies.

In my circuit I have several resistors and fets. Let me take the nwell resistor as an example. The schematic view takes this resistor as a three terminal device, and I connect the body to subc. But LVS indicates discrepancies for all these resistors. I have one p+ contact in the layout, and these are the only LVS errors for this circuit.

The netlist created for the layout seem to be incorrect.
In the source netlist (schematic), I would have
Rnwres2 net2 VSS sub! $[nwres] m=1 r=1.72743K w=3.93u l=10u par=1 sbar=1 mSwitch=0

While in the layout netlist, the resistor becomes
R2 VSS 4 1727.43 L=1e-5 W=3.93e-6 sbar=1 par=1 $SUB=sub! $[nwres] $X=-3360 $Y=210 $D=247

Does anyone know how to fix this problem?

Thanks in advance.
 

Calibre or Assura? If you have multiple-bends resistors you need to use SBAR_Feature (or similar) swicth for Assura.

The second idea is to surround resistors by SwGuardRing (e.g. by multipart path)
 

Calibre or Assura? If you have multiple-bends resistors you need to use SBAR_Feature (or similar) swicth for Assura.

The second idea is to surround resistors by SwGuardRing (e.g. by multipart path)

Hi, I am using Calibre, no multiple-bends. And could you explain more about SwGuardRing?
 

SwGuardRing is a substrate contact. Its made from BP, diffusion and M1 layers. Could you insert a screenshots of your layout and schematic? Without any picture its a bit hard to found where the problem exist.
 

An nwell resistor should (of course) sit in an nwell. Try and connect the 3rd terminal to the nwell tap, and the latter one to VDD (by metal1).
 

SwGuardRing is a substrate contact. Its made from BP, diffusion and M1 layers. Could you insert a screenshots of your layout and schematic? Without any picture its a bit hard to found where the problem exist.



Hi, I have made a test layout. The contact from BP to RX is not shown in this zoom level. Both resisotors do not match with schematic, although their w and l match. Did I make any mistake here?
 

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