flwong
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Dear friends,
I am trying to figure out how many no of bit a DAC is required, of a D8PSK modulation application in a IQ transmitter.
Theoretically, there are only 5 states involved for either positive or negative sign, thus 4bits (1 sign bit is already included) are sufficient. However, the digital signal is passed to SRRC before go to the DAC. May I ask the output of SRRC will affect the number of bit of DAC required? I assume SDFR is not an issue in this case.
Thanks!
flwong
I am trying to figure out how many no of bit a DAC is required, of a D8PSK modulation application in a IQ transmitter.
Theoretically, there are only 5 states involved for either positive or negative sign, thus 4bits (1 sign bit is already included) are sufficient. However, the digital signal is passed to SRRC before go to the DAC. May I ask the output of SRRC will affect the number of bit of DAC required? I assume SDFR is not an issue in this case.
Thanks!
flwong