Every MOSFET carries a BJT inside it. "Taps" are the closest-in
access point for those devices' base resistance. Parasitic SCR
structures which sustain latchup are composed of two BJTs,
at lease one of them needs to be so strongly base-shunted
that it cannot be kept turned on by the current that the (any
local, other) complementary one can throw. This latter, is a
very variable thing and your "tap" distance rules have to
enforce the worst case (unless you want to perform and
believe in, an awfully elaborate and exhaustive TCAD analysis
and get your boss and your customer to buy off on that basis).
If you want to understand, construct yourself an SCR using
foundry models for parasitic BJTs (that's a joke, son) and then
explore how base shunting increases minimum holding current.
Getting to the worst case sensitivity though, that can only
happen post-layout, which is a bit late and effort-consuming
and by that point you really wanted the risk, gone. Start with
taking the rules at face value until you can do better.