Hi everyone, quick question on NPN type outputs and how to filter them.
I'm using a detector device which specifies a NPN output of 250mA.
If I want to interface this to a FPGA as an input, does this mean I have to use a pull-up resistor to 3.3V (my IO voltage) which would be (ie. 4.7k....0.702mA)?
Also, if I want filtering on this input to the FPGA, can I use a decoupling cap to GND such as a 0.1uF?
If I want to interface this to a FPGA as an input, does this mean I have to use a pull-up resistor to 3.3V (my IO voltage) which would be (ie. 4.7k....0.702mA)?
If you want to eliminate short spikes then putting 0.1µF cap in parallel with NPN doesn't help very much ..
Leave the 0.1µF cap on the FPGA pin and add a series resistor (≈1kΩ) between NPN and the pin, and of course the pullup has to be there too ..
for that filter, would the corner frequency fo = 1/(2*pi*RC) = 1.6 kHz approx?
Also, would I expect to see much noise on that line if its open collector? (lets say the the NPN transitor is 50-100 ft away.)
I'm wondering if I will see any noise since, either the NPN will be low (near 0 V), or floating, and the pullup resistor will pull it high with some rise time based on the RC constant.