NPN biasing state in linear regulator

[yefj]

Hello,There is this youtube video of a regulator I saw .
According to the manual the Key in this regulator is the VCE of the BC547C increasing and decreasing according to the current at the base.
What do you think should be the steps to design of the NPN BJT steps?
Thanks.
LTspice file is attached.

 

[D.A.(Tony)Stewart]

It depends what you want for line regulation, load regulation and range of V, I P.

Do you have any ideas on specs?

This design is sub-optimal for many reasons, but you want to learn analog design.
e.g.
1) TO-92 Rja= 200 'C/W with a 12V drop on Q1 and design choice of 50'C rise max. @ max ambient, Pmax = 250 mW at ~21 mA, Although 36.1 °C/W heatsinks exist.

--- Updated Saturday at 7:44 PM ---

The process to choose 12V requires knowing;

1. Zener is 6.2V @ 5mA test current, so using less reduces voltage slightly. (knee resistance ... R*I)
2. Q2 collector current depends on Vbe (quick guess if Ic= 1mA, Vbe = 600 mV)
3. Vbe depends on Thevenin voltage Vth from R divider from 12V and Vz on emitter.
4. The R values minimize current may be computed several ways such as derating hFE min by 50% for cold temperatures for a stable result.

however the quickest way for me would be to simulate in a few minutes for error=2% max.

https://tinyurl.com/2b3ta45y

https://tinyurl.com/26z7vsx5

--- Updated Saturday at 8:30 PM ---

If I was given a fixed load of 1K, then I would simplify as follows. with 180 uA no load @ 12.18V\\https://tinyurl.com/2y9sa555

 

[dick_freebird]

Zener plus the NPN Vbe gives a "fairly flat" TC sum
(if you pick the right bias current, not too much
Rs*Ibias in the mix). Better curvature than a
bandgap (which you wouldn't really want to do
with discretes anyhow).

Know that "stack voltage" and your resistor
divider values can be figured for whatever
voltage output you like (as long as it's above
Vz+Vbe).