The symptoms suggest there is more than one clock pulse and the 'B' input is propagating throughout the whole shft register. The logic levels shouldn't be a problem but noise on signal edges might be, particularly the one shot signal. Just temporarily, try connecting a capacitor (say 100pF) between pins 7 and 8 to see if it improves matters.
Can you confirm something though. You say the CLR input is high but the schematic shows it is floating. Is it actually tied/driven high or are you measuring a logic high with a testmeter? It should be tied high.
Brian.