Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

normal distribution in Verilog-A

Status
Not open for further replies.

crossroad

Newbie level 5
Newbie level 5
Joined
Feb 3, 2007
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,335
In Verilog-A, normal distribution is expressed as $dist_normal(seed,mean, standard variation)
what is "seed" mean??
thanks for the answer
 

The random generator is a pseudorandom generator.
Following excerpt is from the veriloga language manual.

For each system function, the seed parameter is an in-out parameter; that is, a value is
passed to the function and a different value is returned. The system functions will always
return the same value given the same seed. This facilitates debugging by making the
operation of the system repeatable. The argument for the seed parameter should be an
integer variable that is initialized by the user and only updated by the system function.
This will ensure that the desired distribution is achieved.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top