Non overlaping circuit waveform issues

Hi guys,

I've tried several non overlap circuits, just google in images for non overlaping circuits.

Here I present the non overlap circuit done with 2 nand and 1 not then 2 delay lines in each branch.

Picture:



The problem here is that I can't aproximate both the rise and fall edges even more. The only way is to remove the delay lines. Even though if I wish to separate them a bit, using the delay lines it's impossible.

I am using 500Mhz of switching frequency (VPULSE).

Basically the question here is how can I aproximate the edges?

As I said, I did the same with other types os non overlaping circuits but the result is pretty much the same.

Kind regards.

EDIT: If I add more delay (2) the edges get more far away from each other. If I add only one more delay (3) the wave gets a strange shape. It only works with pairs. Why this happens?

If I reduce the size of the transistors in the delay line the signal gets strange because it can't supply current to the nand because of its size.

My tech is UMC130.

There are many variables on controlling Rise and fall time to create "dead-time" in complementary duo or mono outputs.

e.g. geometry of gate w/l ratio, voltage threshold, channel capacitance, drive resistance as well as gate types n or p-type and NOR,NAND

https://www.uib.cat/depart/dfs/GTE/staff/jrossello/articlestesi.pdf?origin=publication_detail

For precision picosecond control, I prefer ECL with variable threshold.

I see. However, I don't know if I am doing well this. aspect rato is 3.2/1u.

I have seen a work where the guys uses something like 10 delay lines. If I do that one of my signal reduces basically to something like a spike or I would say it desapears.

So I wonder if I am doing this right or this is to be done like this,

Regards.

No one here can give a tip?

Hi AMAS84,

In my last project I needed a non-overlapping clock generator for switch control in a SC circuitry. What I found was, that for adjusting dead-time I added additional buffers. I would usually start with minimum size (W/L) transistors and go from there, to control the rise and fall time I made the final inverter/buffer larger or smaller (size (W/L)) depending on what was the final goal. In my experience it was mostly trial and error.

Best of luck Jerry

Hi jerry,

Thanks for the reply.

Can you post here briefly the circuitry that you used?

As you can see in the picture I posted above, I've 2 NAND and one not. Then 2 inverters doing the feedback on each branch.

One thing that I've notice is that as I were inserting more delay lines, the green signal was getting narrower. So I wonder if I am doing right the non overlapping circuit.

When you say that you started with minimum size W/L you mean that I must use the minumum sizes of the W and L and then scaling that value as we go inserting more delays? or the inverter must have a fixed W/L? That is, they must be the same size?

AMSA84 said:

... It only works with pairs. Why this happens?

Click to expand...

Because you need an odd-numbered inversion (180° phase) in total (1 NAND + n pairs of inverters).

AMSA84 said:

I don't know if I am doing well this. aspect rato is 3.2/1u.

Click to expand...

You don't have to cling strictly to such a W/L ratio. Play with it to equalize your rise and fall times.

There are hundreds of ways to control rise time and fall time depending on technology used. You choose the technology to match the requirements.

Variable threshold precision comparators affect both rise and fall time latency. Using dual comparators with independent thresholds one for positive edge and one for negative edge, allows independent control of each edge with a slew rate limited input. THen using logic gating on each edge output can be separated for no-overlapping and precision programmable control using a DAC on the threshold voltage. The most expensive IGBT controllers have this feature of programmable dead-band control for variable reversible bridge loads with a wide range of reactance.

Another way is that using complementary drivers tend to have a differential impedance with N type being lower than P type. Thus N type RC time constants tend to be shorter than P types. Using N type for both Push Pull with complementary gate drivers can alter latency on each edge, and hard to generalize.