Non-Idealities in Delta Sigma Modulator (CT and DT both)

[Eminent.Engineer]

I would like those who have done research on Delta Sigma ADC to answer few questions.
1. What are non-idealities in delta sigma modulator
2. how to model those non-idealities in MATLAB

Kindly post/mail the relevant reading material on eminent.engineer@yahoo.com.
Thanks to all.

 

[micro designer]

as far as non idealities are concerned they are related to integrator such as finite gain,finite bandwidth,offset voltage,slew rate. Comparator non idealities such as offset and non-linearity.
In DT switched capacitor circuit is used therefore there are switches which have finite resistances and non linear capacitors that cause incomplete transfer of charges. switch thermal noise . In relation to clock there is jitter.
This paper will be helpful

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View attachment non ideal sdm.pdf

hope this helps