Noise simulation mismatch from KT/C by fingering the transistor

Hello IC experts,

has anybody before noticed a problem in the transistor thermal noise model as below;

I am simulating ac noise and transient noise for a simple RC circuit, but with the R replaced by a closed (nmos) switch

I am comparing different switches which are vectored, multiplied or fingered nmos, but all have the same W/L total

when transistor is fingered, the resulting noise is up to 2x smaller than KT/C.
for the others, the noise is pretty much KT/C.

my doubt: I would expect gate noise and thus MORE noise than KT/C, but definitely not less!

has anybody experience such a behavior or do you have a reasonable explanation for this problem

BR
Ahmad

ahmad.mar said:

... when transistor is fingered, the resulting noise is up to 2x smaller than KT/C. for the others, the noise is pretty much KT/C...

Click to expand...

In smaller node sizes, thermal gate noise voltage may add a not insignificant contribution to the total thermal noise. The main culprit for this contribution is gate series resistance, and this is much less for fingered transistors than with other configurations.

See also this post.

what you mentioned is true and meaningful, but as I mentioned; my doubt is due to having a noise level below kT/C model, which (kT/C) would be the noise due to the channel resistance only even without the added effect from the gate series resistance!

ahmad.mar said:

... having a noise level below kT/C model, which (kT/C) would be the noise due to the channel resistance only even without the added effect from the gate series resistance!

Click to expand...

This actually isn't easy to be understood. Could the channel resistance calculation be wrong? Any parallel resistances, capacitance short circuits?

erikl said:

Could the channel resistance calculation be wrong? Any parallel resistances, capacitance short circuits?

Click to expand...

the current setup is made very simple to avoid such things, it is basically just a fully on nmos: gate at vdd=1.1, source at some Vdc=0-0.3, drain connected to the capacitor.
The noise power is calculated at the drain.

ahmad.mar said:

nmos: gate at vdd=1.1, source at some Vdc=0-0.3, drain connected to the capacitor.
The noise power is calculated at the drain.

Click to expand...

Where does the drain current flow from? Pls. provide a full schematic!

Ok, thank you. Which C did you use in your calculation? Is it possible that there are more (parallel) capacitances which you didn't consider? Built-in and parasitic ones?

erikl said:

Is it possible that there are more (parallel) capacitances which you didn't consider? Built-in and parasitic ones?

Click to expand...

I think that is not possible, I checked different capacitor sizes (100f - 20pf), and that -wrong- effect seems to scale with the cap size

There may be something to do with how the "fingering"
is done. A MOSFET with W*m*L area might (I suppose)
give a different noise analysis result than (m) W*L MOSFETs
in parallel.

But I also think you may be putting too much weight on
the ideal expression when there are multiple noise actors
and nowhere in that expression do aspects such as gate
resistance appear.

To the point about unexpressed or wrong capacitances,
the sharing of S / D regions in a fingered device will make
some of those smaller than an equivalent width single stripe
device. Whether this is faithfully represented by your subcircuit
and model chain, is an exercise.