tech_enquiryy
Newbie
I am trying to interface a "Pulsed biasing board" with QPA2935 driver amplifier(DA)
Please find the schematic of QPA2935 amplifier below which is the same as given in Applications information section given in the datasheet of QPA2935
Vdd= 25V given to the Power Amplifier.
Test result obtained by interfacing the "Pulsed biasing board" with the amplifier board(QPA2935):-
It can be observed that there is noise in the drain signal. It was observed once it was fed to the Driver Amplifier. There was no noise observed in the drain pulse signal when tested in the "Pulsed biasing board alone" using a resistive load.
We can see that as we are increasing the capacitance value, the noise is decreasing but the falling time is increasing.
This noise in the drain pulse is affecting the gate signal and the RF input fed to the amplifier.
Because of the noise in the rising edge of the RF input, the RF output pulse width is not completely flat. There is a droop.
Below are the images of the observed drain pulse and gate signal (DC) fed to the QPA2935.
Channel 1 (yellow): 5 V drain pulse enable to the "Pulsed biasing board" with pulse period: 100 µs and pulse width: 10 µs (duty cycle = 10%)
Channel 2 (green): Drain pulse output fed to the QPA2935.
Channel 3 (orange): Gate enable(DC) fed to the QPA2935.
Channel 4 (purple): RF input to the QPA2935
The below capacitance values refer to C1 and C3 placed near Vd of the amplifier IC AND R1=R3=10 Ω for both the cases.
1. 1 nF+100 pF capacitors placed near the drain in the Driver Amplifier board.
2. 1 nF+1 nF capacitors placed near the drain in the Driver Amplifier board.
what can be the solution to eliminate this noise?
Please find the attached file for the Pulsed biasing board schematic and QPA2935 datasheet that i am using.
Please find the schematic of QPA2935 amplifier below which is the same as given in Applications information section given in the datasheet of QPA2935
Vdd= 25V given to the Power Amplifier.
Test result obtained by interfacing the "Pulsed biasing board" with the amplifier board(QPA2935):-
It can be observed that there is noise in the drain signal. It was observed once it was fed to the Driver Amplifier. There was no noise observed in the drain pulse signal when tested in the "Pulsed biasing board alone" using a resistive load.
We can see that as we are increasing the capacitance value, the noise is decreasing but the falling time is increasing.
This noise in the drain pulse is affecting the gate signal and the RF input fed to the amplifier.
Because of the noise in the rising edge of the RF input, the RF output pulse width is not completely flat. There is a droop.
Below are the images of the observed drain pulse and gate signal (DC) fed to the QPA2935.
Channel 1 (yellow): 5 V drain pulse enable to the "Pulsed biasing board" with pulse period: 100 µs and pulse width: 10 µs (duty cycle = 10%)
Channel 2 (green): Drain pulse output fed to the QPA2935.
Channel 3 (orange): Gate enable(DC) fed to the QPA2935.
Channel 4 (purple): RF input to the QPA2935
The below capacitance values refer to C1 and C3 placed near Vd of the amplifier IC AND R1=R3=10 Ω for both the cases.
1. 1 nF+100 pF capacitors placed near the drain in the Driver Amplifier board.
2. 1 nF+1 nF capacitors placed near the drain in the Driver Amplifier board.
what can be the solution to eliminate this noise?
Please find the attached file for the Pulsed biasing board schematic and QPA2935 datasheet that i am using.