noise at the output - track and hold

[dkumar]

noise at the output:

HI all,

I have a track and hold followed by a source follower buffer (on silicon) and i have been testing it and seeing the output on an oscilloscope. Attached in one of the outputs i see. It has input signal of 100MHz and sampling frequency is 20MHz ( it is sub-sampling for the purpose of time interleaving architecture in ADC) .

The think that is bothering me is the noise in the hold phase. As far as my understanding goes, the held phase should be a constant value ( and not noisy in the way as it is seen). I am tying to understand from where these might be coming and what i could think of is might be the SF buffer used at the output to derive the pads on chip is adding / making this held value noisy. Or may the switch is not completely turning off and the held phase still contains noise from Ron of switch and input signal.

I am not sure if i am right but is there any way i can analyze it in simulation ?

thanks

 

[karesz]

noise at the output:

Hi dkumar,
For me its a phase starre gating & not sampling, but more interesting is, that whats your noise source?
I think that your circuit has practical realisations problems, as failed bypassing of supplys, not shielded circuit parts and (input)lines, especially sampling C & switch!
Their are "high impedance" parts with higher bandwidth in your circuit, also good receivers for all disturbend signals as (ambient) noises too...
Is your scope probe, for example, installed (for these photo/tests) with only 1-2 cm long GND -loop!?
But why is it not possible for you to test your signal chain (for noise only)from stage to stage pls?
K.