no waveform appear in modelsim

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nursafirah

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i have done the test bench and what so ever.. but my problem is my waveform can't run or generate the wave.. what should i do?
this is my coding.
Code: 
-- Purpose : compress the bit 
-- After reset signal, it will compress the bit output
--input = 001000110 11110000 11011010 00000001 11111010 01101100 00000001 00001000 (64 bit)
--LUT = 00100110 = 00, 11111010 = 01, 01101100 = 10, 00000001 = 11
--output last = 00 11110000 11011010 11 01 10 11 00001000 (33 bit) 


library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all; 

entity compression is

port (	clk			: in std_logic;
	bitout1, bitout4  : buffer std_logic_vector(1 downto 0);
	bitout2, bitout3	: buffer std_logic_vector(7 downto 0); 
	bitin				   : in std_logic_vector (31 downto 0);
	concat_out 			: out std_logic_vector (19 downto 0));
--	a,b,c,d,e,f,g,h									  : in std_logic_vector (7 downto 0);
--   busy				   								  : in std_logic;                        --for clock is '1'
--   not_ready_a 										  : out std_logic;                      --for clock is '0'
--   not_ready_b 										  : out std_logic;  
--   not_ready_c 										  : out std_logic;  
--   not_ready_d 										  : out std_logic);  
 --  not_ready_e 											  : out std_logic;  
--   not_ready_f 											  : out std_logic;  
--   not_ready_g 											  : out std_logic;
 --  not_ready_h 											  : out std_logic);  	
	
end compression;

-----------------------architecture begin-----------------------------------------

architecture SAFIRAH of compression is

	signal conca : std_logic_vector (19 downto 0);
   signal a,b,c,d: std_logic_vector (7 downto 0);

	
BEGIN
process (clk,a)
begin

if (clk='1' and clk'event) then  --clock
		
		a <= bitin (31 downto 24);
		if (a <= "00100110") then
		   bitout1 <= "00";
		elsif (a = "11111010") then
			bitout1 <= "01";
		elsif (a = "01101100") then
			bitout1 <= "10";
		elsif (a = "00000001") then
			bitout1 <= "11";
	--	else
		--(a = std_logic_vector (63 downto 56) <= (others => '-') then
		--	bitout1 (63 downto 56) <= a;
   	end if;
		end if;
	--	end if;
	end process;

	
process (clk,b)
begin
if (clk='1' and clk'event) then
	
	 b <= bitin (23 downto 16);
	 if (b <= "11110000") then 
	     bitout2 <= "11110000"; 
	--if (b <= "00100110") then 
		--   bitout2 <= "00";
		--elsif (b <= "00100110") then
			--bitout2 <= "01";
		--elsif (b <= "00100110") then
			--bitout2 <= "10";
		--elsif (b <= "00100110") then
			--bitout2 <= "11";
	   --else
		--bitout2 <= "111100000";
		end if;
		end if;
	--	end if;
	end process;


process (clk,c)
begin
if (clk='1' and clk'event) then
	
	  c <= bitin (15 downto 8);
		if (c <= "11011010") then 
			bitout3 <= "11011010"; 
	--if (c <= "00100110") then
		--   bitout3 <= "00";
	--	elsif (c <= "00100110") then
		--	bitout3 <= "01";
		--elsif (c <= "00100110") then
		--	bitout3 <= "10";
		--elsif (c <= "00100110") then
		--	bitout3 <= "11";
	--	else
		--	bitout3 <= s;
		end if;
	  end if;
	--	end if;
	end process;	


process (clk,d)
begin
if (clk='1' and clk'event) then
 
  d <= bitin (7 downto 0);
	if (d <= "00100110") then
		   bitout4 <= "00";
		elsif (d <= "11111010") then
			bitout4 <= "01";
		elsif (d <= "01101100") then
			bitout4 <= "10";
		elsif (d <= "00000001") then
			bitout4 <= "11";
--		else
		--	bitout4 <= s;
		end if;
		end if;
	--	end if;
	end process;	


--process (clk,e)
--begin
--if rising_edge (clk) then
--if (busy = '1') then
--	not_ready_e <= '0';
	
--	e <= bitin (31 downto 24);
	--if (e <= "00100110") then
	--	   bitout5 <= "00";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "01";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "10";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "11";
	--   else
		--	bitout5 <= s;
--		end if;
--		end if;
--		end if;
--	end process;


--process (clk,f)
--begin
--if rising_edge (clk) then
--if (busy = '1') then
--	not_ready_f <= '0';
	
--	f <= bitin (23 downto 16);
--	if (f <= "00100110") then
--		   bitout6 <= "00";
--		elsif (f <= "00100110") then
--			bitout6 <= "01";
--		elsif (f = "00100110") then
--			bitout6 <= "10";
--		elsif (f <= "00100110") then
--			bitout6 <= "11";
--	   else
		--	bitout6 <= s;
--		end if;
--		end if;
--		end if;
--	end process;


--process (clk,g)
--begin
--if rising_edge (clk) then
--	if (busy = '1') then
--		not_ready_g <= '0';
		
--	g <= bitin (15 downto 8);
--	   if (g <= "00100110") then
--		   bitout7 <= "00";
--		elsif (g <= "00100110") then
--			bitout7 <= "01";
--		elsif (g <= "00100110") then
--			bitout7 <= "10";
--		elsif (g <= "00100110") then
--			bitout7 <= "11";
--	   else
		--	bitout7 <= s;
--		end if;
--		end if;
--		end if;
--	end process;	


--process (clk,h)
--begin
--if rising_edge (clk) then
--	if (busy = '1') then
--		not_ready_h <= '0';
		
--	h <= bitin (7 downto 0);
--	if (b <= "00001000") then 
	--		bitout8 <= "00001000"; 
	--if (h <= "00100110") then
	--	   bitout8 <= "00";
	--	elsif (h <= "00100110") then
		--	bitout8 <= "01";
	--	elsif (h <= "00100110") then
	--		bitout8 <= "10";
	--	elsif (h <= "00100110") then
	--		bitout8 <= "11";
	--	else 
		--	bitout8 <= s;
	--	end if;
	--	end if;
	--	end if;
--	end process;


---------------------concatenation---------------------------------
 
 
 conca <= bitout1  & bitout2 & bitout3 & bitout4;
 concat_out <= conca;
 
end architecture SAFIRAH;

- - - Updated - - -

and this is my testbench code...
Code: 
LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY compression_vhd_tst IS
END compression_vhd_tst;
ARCHITECTURE compression_arch OF compression_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL bitin : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bitout1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL bitout2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL bitout3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL bitout4 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk : STD_LOGIC := '0';
SIGNAL concat_out : STD_LOGIC_VECTOR(19 DOWNTO 0);
COMPONENT compression
	PORT (
	bitin : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	bitout1 : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
	bitout2 : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
	bitout3 : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
	bitout4 : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
	clk : IN STD_LOGIC;
	concat_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : compression
	PORT MAP (
-- list connections between master ports and signals
	bitin => bitin,
	bitout1 => bitout1,
	bitout2 => bitout2,
	bitout3 => bitout3,
	bitout4 => bitout4,
	clk => clk,
	concat_out => concat_out
	);

--	clk <= not clk after 10ns;
	
--clk_signal : PROCESS

BEGIN                              
		clk <= '0';
		wait for 10ns;
		clk <= '1';
		wait for 10ns;

	end process clk_signal;


--init : PROCESS

--BEGIN
	--	wait for 20ns;
	--	bitin	<= "00100110111100001101101000000001";      
   --   wait for 20ns;
	--	bitin <= "00100110111100001101101000000001";
	--	wait for 20ns;
	--   bitin <= "00100110111100001101101000000001";
	--   wait for 20ns;
	--	bitin <= "00100110111100001101101000000001";
	--	wait for 20ns;
	--	bitin <= "00100110111100001101101000000001";
	--	wait for 20ns;
		
--WAIT;                                                        
--END PROCESS init;                                          
END compression_arch;

- - - Updated - - -

and when i run the modelsim, the error has occur. this is my error. ** Error: (vsim-19) Failed to access library 'compression' at "compression".. what should i do to make it clear?
 

How are you running modelsim? You problem is with the vsim command line which is looking for a compression library. Your code doesn't require that library.

Regards
 

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